-/* Two timers, traditionally steered to PIL's 10 and 14 respectively.
- * But since INO packets are used on sun5, we could use any PIL level
- * we like, however for now we use the normal ones.
- *
- * The 'reg' and 'interrupts' properties for these live in nodes named
- * 'counter-timer'. The first of three 'reg' properties describe where
- * the sun5_timer registers are. The other two I have no idea. (XXX)
- */
-struct sun5_timer {
- u64 count0;
- u64 limit0;
- u64 count1;
- u64 limit1;
-};
-
-#define SUN5_LIMIT_ENABLE 0x80000000
-#define SUN5_LIMIT_TOZERO 0x40000000
-#define SUN5_LIMIT_ZRESTART 0x20000000
-#define SUN5_LIMIT_CMASK 0x1fffffff
-
-/* Given a HZ value, set the limit register to so that the timer IRQ
- * gets delivered that often.
- */
-#define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz))
-