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Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff
[linux-2.6.git]
/
include
/
asm-x86_64
/
tlbflush.h
diff --git
a/include/asm-x86_64/tlbflush.h
b/include/asm-x86_64/tlbflush.h
index
2e811ac
..
4a9c20e
100644
(file)
--- a/
include/asm-x86_64/tlbflush.h
+++ b/
include/asm-x86_64/tlbflush.h
@@
-22,16
+22,18
@@
*/
#define __flush_tlb_global() \
do { \
*/
#define __flush_tlb_global() \
do { \
- unsigned long tmpreg
;
\
+ unsigned long tmpreg
, cr4, cr4_orig;
\
\
__asm__ __volatile__( \
\
__asm__ __volatile__( \
- "movq %1, %%cr4; # turn off PGE \n" \
+ "movq %%cr4, %2; # turn off PGE \n" \
+ "movq %2, %1; \n" \
+ "andq %3, %1; \n" \
+ "movq %1, %%cr4; \n" \
"movq %%cr3, %0; # flush TLB \n" \
"movq %0, %%cr3; \n" \
"movq %2, %%cr4; # turn PGE back on \n" \
"movq %%cr3, %0; # flush TLB \n" \
"movq %0, %%cr3; \n" \
"movq %2, %%cr4; # turn PGE back on \n" \
- : "=&r" (tmpreg) \
- : "r" (mmu_cr4_features & ~X86_CR4_PGE), \
- "r" (mmu_cr4_features) \
+ : "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
+ : "i" (~X86_CR4_PGE) \
: "memory"); \
} while (0)
: "memory"); \
} while (0)
@@
-54,8
+56,9
@@
extern unsigned long pgkern_mask;
* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
*
* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
*
- * ..but the x86_64 has somewhat limited tlb flushing capabilities,
- * and page-granular flushes are available only on i486 and up.
+ * x86-64 can only flush individual pages or full VMs. For a range flush
+ * we always do the full VM. Might be worth trying if for a small
+ * range a few INVLPGs in a row are a win.
*/
#ifndef CONFIG_SMP
*/
#ifndef CONFIG_SMP
@@
-106,6
+109,10
@@
static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
#define TLBSTATE_OK 1
#define TLBSTATE_LAZY 2
#define TLBSTATE_OK 1
#define TLBSTATE_LAZY 2
+/* Roughly an IPI every 20MB with 4k pages for freeing page table
+ ranges. Cost is about 42k of memory for each CPU. */
+#define ARCH_FREE_PTE_NR 5350
+
#endif
#define flush_tlb_kernel_range(start, end) flush_tlb_all()
#endif
#define flush_tlb_kernel_range(start, end) flush_tlb_all()
@@
-113,7
+120,9
@@
static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
- /* x86_64 does not keep any page table caches in TLB */
+ /* x86_64 does not keep any page table caches in a software TLB.
+ The CPUs do in their hardware TLBs, but they are handled
+ by the normal TLB flushing algorithms. */
}
#endif /* _X8664_TLBFLUSH_H */
}
#endif /* _X8664_TLBFLUSH_H */