++void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
++ bool state);
++void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
++
++void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
++void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
++void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);
++
++#endif
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_mac.c linux-2.6.22-10/drivers/net/e1000e/e1000_mac.c
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_mac.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_mac.c 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,1988 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++#include "e1000_hw.h"
++
++/**
++ * e1000_init_mac_ops_generic - Initialize MAC function pointers
++ * @hw: pointer to the HW structure
++ *
++ * Setups up the function pointers to no-op functions
++ **/
++void e1000_init_mac_ops_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ DEBUGFUNC("e1000_init_mac_ops_generic");
++
++ /* General Setup */
++ mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
++ mac->ops.remove_device = e1000_remove_device_generic;
++ mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
++ /* LINK */
++ mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
++ /* Management */
++ mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
++ mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
++ mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
++ /* VLAN, MC, etc. */
++ mac->ops.rar_set = e1000_rar_set_generic;
++ mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
++}
++
++/**
++ * e1000_remove_device_generic - Free device specific structure
++ * @hw: pointer to the HW structure
++ *
++ * If a device specific structure was allocated, this function will
++ * free it.
++ **/
++void e1000_remove_device_generic(struct e1000_hw *hw)
++{
++ DEBUGFUNC("e1000_remove_device_generic");
++
++ /* Freeing the dev_spec member of e1000_hw structure */
++ e1000_free_dev_spec_struct(hw);
++}
++
++/**
++ * e1000_get_bus_info_pcie_generic - Get PCIe bus information
++ * @hw: pointer to the HW structure
++ *
++ * Determines and stores the system bus information for a particular
++ * network interface. The following bus information is determined and stored:
++ * bus speed, bus width, type (PCIe), and PCIe function.
++ **/
++s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
++{
++ struct e1000_bus_info *bus = &hw->bus;
++ s32 ret_val;
++ u32 status;
++ u16 pcie_link_status, pci_header_type;
++
++ DEBUGFUNC("e1000_get_bus_info_pcie_generic");
++
++ bus->type = e1000_bus_type_pci_express;
++ bus->speed = e1000_bus_speed_2500;
++
++ ret_val = e1000_read_pcie_cap_reg(hw,
++ PCIE_LINK_STATUS,
++ &pcie_link_status);
++ if (ret_val)
++ bus->width = e1000_bus_width_unknown;
++ else
++ bus->width = (e1000_bus_width)((pcie_link_status &
++ PCIE_LINK_WIDTH_MASK) >>
++ PCIE_LINK_WIDTH_SHIFT);
++
++ e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
++ if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
++ status = E1000_READ_REG(hw, E1000_STATUS);
++ bus->func = (status & E1000_STATUS_FUNC_MASK)
++ >> E1000_STATUS_FUNC_SHIFT;
++ } else {
++ bus->func = 0;
++ }
++
++ return E1000_SUCCESS;
++}
++
++/**
++ * e1000_clear_vfta_generic - Clear VLAN filter table
++ * @hw: pointer to the HW structure
++ *
++ * Clears the register array which contains the VLAN filter table by
++ * setting all the values to 0.
++ **/
++void e1000_clear_vfta_generic(struct e1000_hw *hw)
++{
++ u32 offset;
++
++ DEBUGFUNC("e1000_clear_vfta_generic");
++
++ for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
++ E1000_WRITE_FLUSH(hw);
++ }
++}
++
++/**
++ * e1000_write_vfta_generic - Write value to VLAN filter table
++ * @hw: pointer to the HW structure
++ * @offset: register offset in VLAN filter table
++ * @value: register value written to VLAN filter table
++ *
++ * Writes value at the given offset in the register array which stores
++ * the VLAN filter table.
++ **/
++void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
++{
++ DEBUGFUNC("e1000_write_vfta_generic");
++
++ E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
++ E1000_WRITE_FLUSH(hw);
++}
++
++/**
++ * e1000_init_rx_addrs_generic - Initialize receive address's
++ * @hw: pointer to the HW structure
++ * @rar_count: receive address registers
++ *
++ * Setups the receive address registers by setting the base receive address
++ * register to the devices MAC address and clearing all the other receive
++ * address registers to 0.
++ **/
++void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
++{
++ u32 i;
++
++ DEBUGFUNC("e1000_init_rx_addrs_generic");
++
++ /* Setup the receive address */
++ DEBUGOUT("Programming MAC Address into RAR[0]\n");
++
++ hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
++
++ /* Zero out the other (rar_entry_count - 1) receive addresses */
++ DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
++ for (i = 1; i < rar_count; i++) {
++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
++ E1000_WRITE_FLUSH(hw);
++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
++ E1000_WRITE_FLUSH(hw);
++ }
++}
++
++/**
++ * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
++ * @hw: pointer to the HW structure
++ *
++ * Checks the nvm for an alternate MAC address. An alternate MAC address
++ * can be setup by pre-boot software and must be treated like a permanent
++ * address and must override the actual permanent MAC address. If an
++ * alternate MAC address is found it is saved in the hw struct and
++ * programmed into RAR0 and the function returns success, otherwise the
++ * function returns an error.
++ **/
++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
++{
++ u32 i;
++ s32 ret_val = E1000_SUCCESS;
++ u16 offset, nvm_alt_mac_addr_offset, nvm_data;
++ u8 alt_mac_addr[ETH_ADDR_LEN];
++
++ DEBUGFUNC("e1000_check_alt_mac_addr_generic");
++
++ ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
++ &nvm_alt_mac_addr_offset);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++
++ if (nvm_alt_mac_addr_offset == 0xFFFF) {
++ ret_val = -(E1000_NOT_IMPLEMENTED);
++ goto out;
++ }
++
++ if (hw->bus.func == E1000_FUNC_1)
++ nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16);
++
++ for (i = 0; i < ETH_ADDR_LEN; i += 2) {
++ offset = nvm_alt_mac_addr_offset + (i >> 1);
++ ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++
++ alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
++ alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
++ }
++
++ /* if multicast bit is set, the alternate address will not be used */
++ if (alt_mac_addr[0] & 0x01) {
++ ret_val = -(E1000_NOT_IMPLEMENTED);
++ goto out;
++ }
++
++ for (i = 0; i < ETH_ADDR_LEN; i++)
++ hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i];
++
++ hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_rar_set_generic - Set receive address register
++ * @hw: pointer to the HW structure
++ * @addr: pointer to the receive address
++ * @index: receive address array register
++ *
++ * Sets the receive address array register at index to the address passed
++ * in by addr.
++ **/
++void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
++{
++ u32 rar_low, rar_high;
++
++ DEBUGFUNC("e1000_rar_set_generic");
++
++ /*
++ * HW expects these in little endian so we reverse the byte order
++ * from network order (big endian) to little endian
++ */
++ rar_low = ((u32) addr[0] |
++ ((u32) addr[1] << 8) |
++ ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
++
++ rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
++
++ /* If MAC address zero, no need to set the AV bit */
++ if (rar_low || rar_high) {
++ if (!hw->mac.disable_av)
++ rar_high |= E1000_RAH_AV;
++ }
++
++ E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
++ E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
++}
++
++/**
++ * e1000_mta_set_generic - Set multicast filter table address
++ * @hw: pointer to the HW structure
++ * @hash_value: determines the MTA register and bit to set
++ *
++ * The multicast table address is a register array of 32-bit registers.
++ * The hash_value is used to determine what register the bit is in, the
++ * current value is read, the new bit is OR'd in and the new value is
++ * written back into the register.
++ **/
++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
++{
++ u32 hash_bit, hash_reg, mta;
++
++ DEBUGFUNC("e1000_mta_set_generic");
++ /*
++ * The MTA is a register array of 32-bit registers. It is
++ * treated like an array of (32*mta_reg_count) bits. We want to
++ * set bit BitArray[hash_value]. So we figure out what register
++ * the bit is in, read it, OR in the new bit, then write
++ * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
++ * mask to bits 31:5 of the hash value which gives us the
++ * register we're modifying. The hash bit within that register
++ * is determined by the lower 5 bits of the hash value.
++ */
++ hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
++ hash_bit = hash_value & 0x1F;
++
++ mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
++
++ mta |= (1 << hash_bit);
++
++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
++ E1000_WRITE_FLUSH(hw);
++}
++
++/**
++ * e1000_update_mc_addr_list_generic - Update Multicast addresses
++ * @hw: pointer to the HW structure
++ * @mc_addr_list: array of multicast addresses to program
++ * @mc_addr_count: number of multicast addresses to program
++ * @rar_used_count: the first RAR register free to program
++ * @rar_count: total number of supported Receive Address Registers
++ *
++ * Updates the Receive Address Registers and Multicast Table Array.
++ * The caller must have a packed mc_addr_list of multicast addresses.
++ * The parameter rar_count will usually be hw->mac.rar_entry_count
++ * unless there are workarounds that change this.
++ **/
++void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
++ u8 *mc_addr_list, u32 mc_addr_count,
++ u32 rar_used_count, u32 rar_count)
++{
++ u32 hash_value;
++ u32 i;
++
++ DEBUGFUNC("e1000_update_mc_addr_list_generic");
++
++ /*
++ * Load the first set of multicast addresses into the exact
++ * filters (RAR). If there are not enough to fill the RAR
++ * array, clear the filters.
++ */
++ for (i = rar_used_count; i < rar_count; i++) {
++ if (mc_addr_count) {
++ hw->mac.ops.rar_set(hw, mc_addr_list, i);
++ mc_addr_count--;
++ mc_addr_list += ETH_ADDR_LEN;
++ } else {
++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
++ E1000_WRITE_FLUSH(hw);
++ E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
++ E1000_WRITE_FLUSH(hw);
++ }
++ }
++
++ /* Clear the old settings from the MTA */
++ DEBUGOUT("Clearing MTA\n");
++ for (i = 0; i < hw->mac.mta_reg_count; i++) {
++ E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
++ E1000_WRITE_FLUSH(hw);
++ }
++
++ /* Load any remaining multicast addresses into the hash table. */
++ for (; mc_addr_count > 0; mc_addr_count--) {
++ hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
++ DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
++ hw->mac.ops.mta_set(hw, hash_value);
++ mc_addr_list += ETH_ADDR_LEN;
++ }
++}
++
++/**
++ * e1000_hash_mc_addr_generic - Generate a multicast hash value
++ * @hw: pointer to the HW structure
++ * @mc_addr: pointer to a multicast address
++ *
++ * Generates a multicast address hash value which is used to determine
++ * the multicast filter table array address and new table value. See
++ * e1000_mta_set_generic()
++ **/
++u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
++{
++ u32 hash_value, hash_mask;
++ u8 bit_shift = 0;
++
++ DEBUGFUNC("e1000_hash_mc_addr_generic");
++
++ /* Register count multiplied by bits per register */
++ hash_mask = (hw->mac.mta_reg_count * 32) - 1;
++
++ /*
++ * For a mc_filter_type of 0, bit_shift is the number of left-shifts
++ * where 0xFF would still fall within the hash mask.
++ */
++ while (hash_mask >> bit_shift != 0xFF)
++ bit_shift++;
++
++ /*
++ * The portion of the address that is used for the hash table
++ * is determined by the mc_filter_type setting.
++ * The algorithm is such that there is a total of 8 bits of shifting.
++ * The bit_shift for a mc_filter_type of 0 represents the number of
++ * left-shifts where the MSB of mc_addr[5] would still fall within
++ * the hash_mask. Case 0 does this exactly. Since there are a total
++ * of 8 bits of shifting, then mc_addr[4] will shift right the
++ * remaining number of bits. Thus 8 - bit_shift. The rest of the
++ * cases are a variation of this algorithm...essentially raising the
++ * number of bits to shift mc_addr[5] left, while still keeping the
++ * 8-bit shifting total.
++ *
++ * For example, given the following Destination MAC Address and an
++ * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
++ * we can see that the bit_shift for case 0 is 4. These are the hash
++ * values resulting from each mc_filter_type...
++ * [0] [1] [2] [3] [4] [5]
++ * 01 AA 00 12 34 56
++ * LSB MSB
++ *
++ * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
++ * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
++ * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
++ * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
++ */
++ switch (hw->mac.mc_filter_type) {
++ default:
++ case 0:
++ break;
++ case 1:
++ bit_shift += 1;
++ break;
++ case 2:
++ bit_shift += 2;
++ break;
++ case 3:
++ bit_shift += 4;
++ break;
++ }
++
++ hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
++ (((u16) mc_addr[5]) << bit_shift)));
++
++ return hash_value;
++}
++
++/**
++ * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
++ * @hw: pointer to the HW structure
++ *
++ * Clears the base hardware counters by reading the counter registers.
++ **/
++void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
++{
++ volatile u32 temp;
++
++ DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
++
++ temp = E1000_READ_REG(hw, E1000_CRCERRS);
++ temp = E1000_READ_REG(hw, E1000_SYMERRS);
++ temp = E1000_READ_REG(hw, E1000_MPC);
++ temp = E1000_READ_REG(hw, E1000_SCC);
++ temp = E1000_READ_REG(hw, E1000_ECOL);
++ temp = E1000_READ_REG(hw, E1000_MCC);
++ temp = E1000_READ_REG(hw, E1000_LATECOL);
++ temp = E1000_READ_REG(hw, E1000_COLC);
++ temp = E1000_READ_REG(hw, E1000_DC);
++ temp = E1000_READ_REG(hw, E1000_SEC);
++ temp = E1000_READ_REG(hw, E1000_RLEC);
++ temp = E1000_READ_REG(hw, E1000_XONRXC);
++ temp = E1000_READ_REG(hw, E1000_XONTXC);
++ temp = E1000_READ_REG(hw, E1000_XOFFRXC);
++ temp = E1000_READ_REG(hw, E1000_XOFFTXC);
++ temp = E1000_READ_REG(hw, E1000_FCRUC);
++ temp = E1000_READ_REG(hw, E1000_GPRC);
++ temp = E1000_READ_REG(hw, E1000_BPRC);
++ temp = E1000_READ_REG(hw, E1000_MPRC);
++ temp = E1000_READ_REG(hw, E1000_GPTC);
++ temp = E1000_READ_REG(hw, E1000_GORCL);
++ temp = E1000_READ_REG(hw, E1000_GORCH);
++ temp = E1000_READ_REG(hw, E1000_GOTCL);
++ temp = E1000_READ_REG(hw, E1000_GOTCH);
++ temp = E1000_READ_REG(hw, E1000_RNBC);
++ temp = E1000_READ_REG(hw, E1000_RUC);
++ temp = E1000_READ_REG(hw, E1000_RFC);
++ temp = E1000_READ_REG(hw, E1000_ROC);
++ temp = E1000_READ_REG(hw, E1000_RJC);
++ temp = E1000_READ_REG(hw, E1000_TORL);
++ temp = E1000_READ_REG(hw, E1000_TORH);
++ temp = E1000_READ_REG(hw, E1000_TOTL);
++ temp = E1000_READ_REG(hw, E1000_TOTH);
++ temp = E1000_READ_REG(hw, E1000_TPR);
++ temp = E1000_READ_REG(hw, E1000_TPT);
++ temp = E1000_READ_REG(hw, E1000_MPTC);
++ temp = E1000_READ_REG(hw, E1000_BPTC);
++}
++
++/**
++ * e1000_check_for_copper_link_generic - Check for link (Copper)
++ * @hw: pointer to the HW structure
++ *
++ * Checks to see of the link status of the hardware has changed. If a
++ * change in link status has been detected, then we read the PHY registers
++ * to get the current speed/duplex if link exists.
++ **/
++s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ s32 ret_val;
++ bool link;
++
++ DEBUGFUNC("e1000_check_for_copper_link");
++
++ /*
++ * We only want to go out to the PHY registers to see if Auto-Neg
++ * has completed and/or if our link status has changed. The
++ * get_link_status flag is set upon receiving a Link Status
++ * Change or Rx Sequence Error interrupt.
++ */
++ if (!mac->get_link_status) {
++ ret_val = E1000_SUCCESS;
++ goto out;
++ }
++
++ /*
++ * First we want to see if the MII Status Register reports
++ * link. If so, then we want to get the current speed/duplex
++ * of the PHY.
++ */
++ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
++ if (ret_val)
++ goto out;
++
++ if (!link)
++ goto out; /* No link detected */
++
++ mac->get_link_status = false;
++
++ /*
++ * Check if there was DownShift, must be checked
++ * immediately after link-up
++ */
++ e1000_check_downshift_generic(hw);
++
++ /*
++ * If we are forcing speed/duplex, then we simply return since
++ * we have already determined whether we have link or not.
++ */
++ if (!mac->autoneg) {
++ ret_val = -E1000_ERR_CONFIG;
++ goto out;
++ }
++
++ /*
++ * Auto-Neg is enabled. Auto Speed Detection takes care
++ * of MAC speed/duplex configuration. So we only need to
++ * configure Collision Distance in the MAC.
++ */
++ e1000_config_collision_dist_generic(hw);
++
++ /*
++ * Configure Flow Control now that Auto-Neg has completed.
++ * First, we need to restore the desired flow control
++ * settings because we may have had to re-autoneg with a
++ * different link partner.
++ */
++ ret_val = e1000_config_fc_after_link_up_generic(hw);
++ if (ret_val) {
++ DEBUGOUT("Error configuring flow control\n");
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_check_for_fiber_link_generic - Check for link (Fiber)
++ * @hw: pointer to the HW structure
++ *
++ * Checks for link up on the hardware. If link is not up and we have
++ * a signal, then we need to force link up.
++ **/
++s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ u32 rxcw;
++ u32 ctrl;
++ u32 status;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_check_for_fiber_link_generic");
++
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++ status = E1000_READ_REG(hw, E1000_STATUS);
++ rxcw = E1000_READ_REG(hw, E1000_RXCW);
++
++ /*
++ * If we don't have link (auto-negotiation failed or link partner
++ * cannot auto-negotiate), the cable is plugged in (we have signal),
++ * and our link partner is not trying to auto-negotiate with us (we
++ * are receiving idles or data), we need to force link up. We also
++ * need to give auto-negotiation time to complete, in case the cable
++ * was just plugged in. The autoneg_failed flag does this.
++ */
++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
++ if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
++ (!(rxcw & E1000_RXCW_C))) {
++ if (mac->autoneg_failed == 0) {
++ mac->autoneg_failed = 1;
++ goto out;
++ }
++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
++
++ /* Disable auto-negotiation in the TXCW register */
++ E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
++
++ /* Force link-up and also force full-duplex. */
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
++
++ /* Configure Flow Control after forcing link up. */
++ ret_val = e1000_config_fc_after_link_up_generic(hw);
++ if (ret_val) {
++ DEBUGOUT("Error configuring flow control\n");
++ goto out;
++ }
++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
++ /*
++ * If we are forcing link and we are receiving /C/ ordered
++ * sets, re-enable auto-negotiation in the TXCW register
++ * and disable forced link in the Device Control register
++ * in an attempt to auto-negotiate with our link partner.
++ */
++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
++ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
++
++ mac->serdes_has_link = true;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_check_for_serdes_link_generic - Check for link (Serdes)
++ * @hw: pointer to the HW structure
++ *
++ * Checks for link up on the hardware. If link is not up and we have
++ * a signal, then we need to force link up.
++ **/
++s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ u32 rxcw;
++ u32 ctrl;
++ u32 status;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_check_for_serdes_link_generic");
++
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++ status = E1000_READ_REG(hw, E1000_STATUS);
++ rxcw = E1000_READ_REG(hw, E1000_RXCW);
++
++ /*
++ * If we don't have link (auto-negotiation failed or link partner
++ * cannot auto-negotiate), and our link partner is not trying to
++ * auto-negotiate with us (we are receiving idles or data),
++ * we need to force link up. We also need to give auto-negotiation
++ * time to complete.
++ */
++ /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
++ if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
++ if (mac->autoneg_failed == 0) {
++ mac->autoneg_failed = 1;
++ goto out;
++ }
++ DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
++
++ /* Disable auto-negotiation in the TXCW register */
++ E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
++
++ /* Force link-up and also force full-duplex. */
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++ ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
++
++ /* Configure Flow Control after forcing link up. */
++ ret_val = e1000_config_fc_after_link_up_generic(hw);
++ if (ret_val) {
++ DEBUGOUT("Error configuring flow control\n");
++ goto out;
++ }
++ } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
++ /*
++ * If we are forcing link and we are receiving /C/ ordered
++ * sets, re-enable auto-negotiation in the TXCW register
++ * and disable forced link in the Device Control register
++ * in an attempt to auto-negotiate with our link partner.
++ */
++ DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
++ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
++ E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
++
++ mac->serdes_has_link = true;
++ } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
++ /*
++ * If we force link for non-auto-negotiation switch, check
++ * link status based on MAC synchronization for internal
++ * serdes media type.
++ */
++ /* SYNCH bit and IV bit are sticky. */
++ usec_delay(10);
++ rxcw = E1000_READ_REG(hw, E1000_RXCW);
++ if (rxcw & E1000_RXCW_SYNCH) {
++ if (!(rxcw & E1000_RXCW_IV)) {
++ mac->serdes_has_link = true;
++ DEBUGOUT("SERDES: Link up - forced.\n");
++ }
++ } else {
++ mac->serdes_has_link = false;
++ DEBUGOUT("SERDES: Link down - force failed.\n");
++ }
++ }
++
++ if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
++ status = E1000_READ_REG(hw, E1000_STATUS);
++ if (status & E1000_STATUS_LU) {
++ /* SYNCH bit and IV bit are sticky, so reread rxcw. */
++ usec_delay(10);
++ rxcw = E1000_READ_REG(hw, E1000_RXCW);
++ if (rxcw & E1000_RXCW_SYNCH) {
++ if (!(rxcw & E1000_RXCW_IV)) {
++ mac->serdes_has_link = TRUE;
++ DEBUGOUT("SERDES: Link up - autoneg "
++ "completed sucessfully.\n");
++ } else {
++ mac->serdes_has_link = FALSE;
++ DEBUGOUT("SERDES: Link down - invalid"
++ "codewords detected in autoneg.\n");
++ }
++ } else {
++ mac->serdes_has_link = FALSE;
++ DEBUGOUT("SERDES: Link down - no sync.\n");
++ }
++ } else {
++ mac->serdes_has_link = FALSE;
++ DEBUGOUT("SERDES: Link down - autoneg failed\n");
++ }
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_setup_link_generic - Setup flow control and link settings
++ * @hw: pointer to the HW structure
++ *
++ * Determines which flow control settings to use, then configures flow
++ * control. Calls the appropriate media-specific link configuration
++ * function. Assuming the adapter has a valid link partner, a valid link
++ * should be established. Assumes the hardware has previously been reset
++ * and the transmitter and receiver are not enabled.
++ **/
++s32 e1000_setup_link_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_setup_link_generic");
++
++ /*
++ * In the case of the phy reset being blocked, we already have a link.
++ * We do not need to set it up again.
++ */
++ if (hw->phy.ops.check_reset_block)
++ if (hw->phy.ops.check_reset_block(hw))
++ goto out;
++
++ /*
++ * If flow control is set to default, set flow control based on
++ * the EEPROM flow control settings.
++ */
++ if (hw->fc.type == e1000_fc_default) {
++ ret_val = e1000_set_default_fc_generic(hw);
++ if (ret_val)
++ goto out;
++ }
++
++ /*
++ * We want to save off the original Flow Control configuration just
++ * in case we get disconnected and then reconnected into a different
++ * hub or switch with different Flow Control capabilities.
++ */
++ hw->fc.original_type = hw->fc.type;
++
++ DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
++
++ /* Call the necessary media_type subroutine to configure the link. */
++ ret_val = hw->mac.ops.setup_physical_interface(hw);
++ if (ret_val)
++ goto out;
++
++ /*
++ * Initialize the flow control address, type, and PAUSE timer
++ * registers to their default values. This is done even if flow
++ * control is disabled, because it does not hurt anything to
++ * initialize these registers.
++ */
++ DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
++ E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
++ E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
++ E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
++
++ E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
++
++ ret_val = e1000_set_fc_watermarks_generic(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
++ * @hw: pointer to the HW structure
++ *
++ * Configures collision distance and flow control for fiber and serdes
++ * links. Upon successful setup, poll for link.
++ **/
++s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
++{
++ u32 ctrl;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
++
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++
++ /* Take the link out of reset */
++ ctrl &= ~E1000_CTRL_LRST;
++
++ e1000_config_collision_dist_generic(hw);
++
++ ret_val = e1000_commit_fc_settings_generic(hw);
++ if (ret_val)
++ goto out;
++
++ /*
++ * Since auto-negotiation is enabled, take the link out of reset (the
++ * link will be in reset, because we previously reset the chip). This
++ * will restart auto-negotiation. If auto-negotiation is successful
++ * then the link-up status bit will be set and the flow control enable
++ * bits (RFCE and TFCE) will be set according to their negotiated value.
++ */
++ DEBUGOUT("Auto-negotiation enabled\n");
++
++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
++ E1000_WRITE_FLUSH(hw);
++ msec_delay(1);
++
++ /*
++ * For these adapters, the SW definable pin 1 is set when the optics
++ * detect a signal. If we have a signal, then poll for a "Link-Up"
++ * indication.
++ */
++ if (hw->phy.media_type == e1000_media_type_internal_serdes ||
++ (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
++ ret_val = e1000_poll_fiber_serdes_link_generic(hw);
++ } else {
++ DEBUGOUT("No signal detected\n");
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_config_collision_dist_generic - Configure collision distance
++ * @hw: pointer to the HW structure
++ *
++ * Configures the collision distance to the default value and is used
++ * during link setup. Currently no func pointer exists and all
++ * implementations are handled in the generic version of this function.
++ **/
++void e1000_config_collision_dist_generic(struct e1000_hw *hw)
++{
++ u32 tctl;
++
++ DEBUGFUNC("e1000_config_collision_dist_generic");
++
++ tctl = E1000_READ_REG(hw, E1000_TCTL);
++
++ tctl &= ~E1000_TCTL_COLD;
++ tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
++
++ E1000_WRITE_REG(hw, E1000_TCTL, tctl);
++ E1000_WRITE_FLUSH(hw);
++}
++
++/**
++ * e1000_poll_fiber_serdes_link_generic - Poll for link up
++ * @hw: pointer to the HW structure
++ *
++ * Polls for link up by reading the status register, if link fails to come
++ * up with auto-negotiation, then the link is forced if a signal is detected.
++ **/
++s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ u32 i, status;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
++
++ /*
++ * If we have a signal (the cable is plugged in, or assumed true for
++ * serdes media) then poll for a "Link-Up" indication in the Device
++ * Status Register. Time-out if a link isn't seen in 500 milliseconds
++ * seconds (Auto-negotiation should complete in less than 500
++ * milliseconds even if the other end is doing it in SW).
++ */
++ for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
++ msec_delay(10);
++ status = E1000_READ_REG(hw, E1000_STATUS);
++ if (status & E1000_STATUS_LU)
++ break;
++ }
++ if (i == FIBER_LINK_UP_LIMIT) {
++ DEBUGOUT("Never got a valid link from auto-neg!!!\n");
++ mac->autoneg_failed = 1;
++ /*
++ * AutoNeg failed to achieve a link, so we'll call
++ * mac->check_for_link. This routine will force the
++ * link up if we detect a signal. This will allow us to
++ * communicate with non-autonegotiating link partners.
++ */
++ ret_val = hw->mac.ops.check_for_link(hw);
++ if (ret_val) {
++ DEBUGOUT("Error while checking for link\n");
++ goto out;
++ }
++ mac->autoneg_failed = 0;
++ } else {
++ mac->autoneg_failed = 0;
++ DEBUGOUT("Valid Link Found\n");
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_commit_fc_settings_generic - Configure flow control
++ * @hw: pointer to the HW structure
++ *
++ * Write the flow control settings to the Transmit Config Word Register (TXCW)
++ * base on the flow control settings in e1000_mac_info.
++ **/
++s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ u32 txcw;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_commit_fc_settings_generic");
++
++ /*
++ * Check for a software override of the flow control settings, and
++ * setup the device accordingly. If auto-negotiation is enabled, then
++ * software will have to set the "PAUSE" bits to the correct value in
++ * the Transmit Config Word Register (TXCW) and re-start auto-
++ * negotiation. However, if auto-negotiation is disabled, then
++ * software will have to manually configure the two flow control enable
++ * bits in the CTRL register.
++ *
++ * The possible values of the "fc" parameter are:
++ * 0: Flow control is completely disabled
++ * 1: Rx flow control is enabled (we can receive pause frames,
++ * but not send pause frames).
++ * 2: Tx flow control is enabled (we can send pause frames but we
++ * do not support receiving pause frames).
++ * 3: Both Rx and Tx flow control (symmetric) are enabled.
++ */
++ switch (hw->fc.type) {
++ case e1000_fc_none:
++ /* Flow control completely disabled by a software over-ride. */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
++ break;
++ case e1000_fc_rx_pause:
++ /*
++ * Rx Flow control is enabled and Tx Flow control is disabled
++ * by a software over-ride. Since there really isn't a way to
++ * advertise that we are capable of Rx Pause ONLY, we will
++ * advertise that we support both symmetric and asymmetric RX
++ * PAUSE. Later, we will disable the adapter's ability to send
++ * PAUSE frames.
++ */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
++ break;
++ case e1000_fc_tx_pause:
++ /*
++ * Tx Flow control is enabled, and Rx Flow control is disabled,
++ * by a software over-ride.
++ */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
++ break;
++ case e1000_fc_full:
++ /*
++ * Flow control (both Rx and Tx) is enabled by a software
++ * over-ride.
++ */
++ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
++ break;
++ default:
++ DEBUGOUT("Flow control param set incorrectly\n");
++ ret_val = -E1000_ERR_CONFIG;
++ goto out;
++ break;
++ }
++
++ E1000_WRITE_REG(hw, E1000_TXCW, txcw);
++ mac->txcw = txcw;
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
++ * @hw: pointer to the HW structure
++ *
++ * Sets the flow control high/low threshold (watermark) registers. If
++ * flow control XON frame transmission is enabled, then set XON frame
++ * transmission as well.
++ **/
++s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++ u32 fcrtl = 0, fcrth = 0;
++
++ DEBUGFUNC("e1000_set_fc_watermarks_generic");
++
++ /*
++ * Set the flow control receive threshold registers. Normally,
++ * these registers will be set to a default threshold that may be
++ * adjusted later by the driver's runtime code. However, if the
++ * ability to transmit pause frames is not enabled, then these
++ * registers will be set to 0.
++ */
++ if (hw->fc.type & e1000_fc_tx_pause) {
++ /*
++ * We need to set up the Receive Threshold high and low water
++ * marks as well as (optionally) enabling the transmission of
++ * XON frames.
++ */
++ fcrtl = hw->fc.low_water;
++ if (hw->fc.send_xon)
++ fcrtl |= E1000_FCRTL_XONE;
++
++ fcrth = hw->fc.high_water;
++ }
++ E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
++ E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
++
++ return ret_val;
++}
++
++/**
++ * e1000_set_default_fc_generic - Set flow control default values
++ * @hw: pointer to the HW structure
++ *
++ * Read the EEPROM for the default values for flow control and store the
++ * values.
++ **/
++s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++ u16 nvm_data;
++
++ DEBUGFUNC("e1000_set_default_fc_generic");
++
++ /*
++ * Read and store word 0x0F of the EEPROM. This word contains bits
++ * that determine the hardware's default PAUSE (flow control) mode,
++ * a bit that determines whether the HW defaults to enabling or
++ * disabling auto-negotiation, and the direction of the
++ * SW defined pins. If there is no SW over-ride of the flow
++ * control setting, then the variable hw->fc will
++ * be initialized based on a value in the EEPROM.
++ */
++ ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
++
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++
++ if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
++ hw->fc.type = e1000_fc_none;
++ else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
++ NVM_WORD0F_ASM_DIR)
++ hw->fc.type = e1000_fc_tx_pause;
++ else
++ hw->fc.type = e1000_fc_full;
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_force_mac_fc_generic - Force the MAC's flow control settings
++ * @hw: pointer to the HW structure
++ *
++ * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
++ * device control register to reflect the adapter settings. TFCE and RFCE
++ * need to be explicitly set by software when a copper PHY is used because
++ * autonegotiation is managed by the PHY rather than the MAC. Software must
++ * also configure these bits when link is forced on a fiber connection.
++ **/
++s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
++{
++ u32 ctrl;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_force_mac_fc_generic");
++
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++
++ /*
++ * Because we didn't get link via the internal auto-negotiation
++ * mechanism (we either forced link or we got link via PHY
++ * auto-neg), we have to manually enable/disable transmit an
++ * receive flow control.
++ *
++ * The "Case" statement below enables/disable flow control
++ * according to the "hw->fc.type" parameter.
++ *
++ * The possible values of the "fc" parameter are:
++ * 0: Flow control is completely disabled
++ * 1: Rx flow control is enabled (we can receive pause
++ * frames but not send pause frames).
++ * 2: Tx flow control is enabled (we can send pause frames
++ * frames but we do not receive pause frames).
++ * 3: Both Rx and Tx flow control (symmetric) is enabled.
++ * other: No other values should be possible at this point.
++ */
++ DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type);
++
++ switch (hw->fc.type) {
++ case e1000_fc_none:
++ ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
++ break;
++ case e1000_fc_rx_pause:
++ ctrl &= (~E1000_CTRL_TFCE);
++ ctrl |= E1000_CTRL_RFCE;
++ break;
++ case e1000_fc_tx_pause:
++ ctrl &= (~E1000_CTRL_RFCE);
++ ctrl |= E1000_CTRL_TFCE;
++ break;
++ case e1000_fc_full:
++ ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
++ break;
++ default:
++ DEBUGOUT("Flow control param set incorrectly\n");
++ ret_val = -E1000_ERR_CONFIG;
++ goto out;
++ }
++
++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_config_fc_after_link_up_generic - Configures flow control after link
++ * @hw: pointer to the HW structure
++ *
++ * Checks the status of auto-negotiation after link up to ensure that the
++ * speed and duplex were not forced. If the link needed to be forced, then
++ * flow control needs to be forced also. If auto-negotiation is enabled
++ * and did not fail, then we configure flow control based on our link
++ * partner.
++ **/
++s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ struct e1000_phy_info *phy = &hw->phy;
++ s32 ret_val = E1000_SUCCESS;
++ u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
++ u16 speed, duplex;
++
++ DEBUGFUNC("e1000_config_fc_after_link_up_generic");
++
++ /*
++ * Check for the case where we have fiber media and auto-neg failed
++ * so we had to force link. In this case, we need to force the
++ * configuration of the MAC to match the "fc" parameter.
++ */
++ if (mac->autoneg_failed) {
++ if (hw->phy.media_type == e1000_media_type_fiber ||
++ hw->phy.media_type == e1000_media_type_internal_serdes)
++ ret_val = e1000_force_mac_fc_generic(hw);
++ } else {
++ if (hw->phy.media_type == e1000_media_type_copper)
++ ret_val = e1000_force_mac_fc_generic(hw);
++ }
++
++ if (ret_val) {
++ DEBUGOUT("Error forcing flow control settings\n");
++ goto out;
++ }
++
++ /*
++ * Check for the case where we have copper media and auto-neg is
++ * enabled. In this case, we need to check and see if Auto-Neg
++ * has completed, and if so, how the PHY and link partner has
++ * flow control configured.
++ */
++ if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
++ /*
++ * Read the MII Status Register and check to see if AutoNeg
++ * has completed. We read this twice because this reg has
++ * some "sticky" (latched) bits.
++ */
++ ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
++ if (ret_val)
++ goto out;
++ ret_val = phy->ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
++ if (ret_val)
++ goto out;
++
++ if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
++ DEBUGOUT("Copper PHY and Auto Neg "
++ "has not completed.\n");
++ goto out;
++ }
++
++ /*
++ * The AutoNeg process has completed, so we now need to
++ * read both the Auto Negotiation Advertisement
++ * Register (Address 4) and the Auto_Negotiation Base
++ * Page Ability Register (Address 5) to determine how
++ * flow control was negotiated.
++ */
++ ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV,
++ &mii_nway_adv_reg);
++ if (ret_val)
++ goto out;
++ ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY,
++ &mii_nway_lp_ability_reg);
++ if (ret_val)
++ goto out;
++
++ /*
++ * Two bits in the Auto Negotiation Advertisement Register
++ * (Address 4) and two bits in the Auto Negotiation Base
++ * Page Ability Register (Address 5) determine flow control
++ * for both the PHY and the link partner. The following
++ * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
++ * 1999, describes these PAUSE resolution bits and how flow
++ * control is determined based upon these settings.
++ * NOTE: DC = Don't Care
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
++ *-------|---------|-------|---------|--------------------
++ * 0 | 0 | DC | DC | e1000_fc_none
++ * 0 | 1 | 0 | DC | e1000_fc_none
++ * 0 | 1 | 1 | 0 | e1000_fc_none
++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
++ * 1 | 0 | 0 | DC | e1000_fc_none
++ * 1 | DC | 1 | DC | e1000_fc_full
++ * 1 | 1 | 0 | 0 | e1000_fc_none
++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
++ *
++ * Are both PAUSE bits set to 1? If so, this implies
++ * Symmetric Flow Control is enabled at both ends. The
++ * ASM_DIR bits are irrelevant per the spec.
++ *
++ * For Symmetric Flow Control:
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
++ *-------|---------|-------|---------|--------------------
++ * 1 | DC | 1 | DC | E1000_fc_full
++ *
++ */
++ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
++ /*
++ * Now we need to check if the user selected Rx ONLY
++ * of pause frames. In this case, we had to advertise
++ * FULL flow control because we could not advertise RX
++ * ONLY. Hence, we must now check to see if we need to
++ * turn OFF the TRANSMISSION of PAUSE frames.
++ */
++ if (hw->fc.original_type == e1000_fc_full) {
++ hw->fc.type = e1000_fc_full;
++ DEBUGOUT("Flow Control = FULL.\r\n");
++ } else {
++ hw->fc.type = e1000_fc_rx_pause;
++ DEBUGOUT("Flow Control = "
++ "RX PAUSE frames only.\r\n");
++ }
++ }
++ /*
++ * For receiving PAUSE frames ONLY.
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
++ *-------|---------|-------|---------|--------------------
++ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
++ */
++ else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
++ hw->fc.type = e1000_fc_tx_pause;
++ DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
++ }
++ /*
++ * For transmitting PAUSE frames ONLY.
++ *
++ * LOCAL DEVICE | LINK PARTNER
++ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
++ *-------|---------|-------|---------|--------------------
++ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
++ */
++ else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
++ (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
++ !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
++ (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
++ hw->fc.type = e1000_fc_rx_pause;
++ DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
++ } else {
++ /*
++ * Per the IEEE spec, at this point flow control
++ * should be disabled.
++ */
++ hw->fc.type = e1000_fc_none;
++ DEBUGOUT("Flow Control = NONE.\r\n");
++ }
++
++ /*
++ * Now we need to do one last check... If we auto-
++ * negotiated to HALF DUPLEX, flow control should not be
++ * enabled per IEEE 802.3 spec.
++ */
++ ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
++ if (ret_val) {
++ DEBUGOUT("Error getting link speed and duplex\n");
++ goto out;
++ }
++
++ if (duplex == HALF_DUPLEX)
++ hw->fc.type = e1000_fc_none;
++
++ /*
++ * Now we call a subroutine to actually force the MAC
++ * controller to use the correct flow control settings.
++ */
++ ret_val = e1000_force_mac_fc_generic(hw);
++ if (ret_val) {
++ DEBUGOUT("Error forcing flow control settings\n");
++ goto out;
++ }
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
++ * @hw: pointer to the HW structure
++ * @speed: stores the current speed
++ * @duplex: stores the current duplex
++ *
++ * Read the status register for the current speed/duplex and store the current
++ * speed and duplex for copper connections.
++ **/
++s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
++ u16 *duplex)
++{
++ u32 status;
++
++ DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
++
++ status = E1000_READ_REG(hw, E1000_STATUS);
++ if (status & E1000_STATUS_SPEED_1000) {
++ *speed = SPEED_1000;
++ DEBUGOUT("1000 Mbs, ");
++ } else if (status & E1000_STATUS_SPEED_100) {
++ *speed = SPEED_100;
++ DEBUGOUT("100 Mbs, ");
++ } else {
++ *speed = SPEED_10;
++ DEBUGOUT("10 Mbs, ");
++ }
++
++ if (status & E1000_STATUS_FD) {
++ *duplex = FULL_DUPLEX;
++ DEBUGOUT("Full Duplex\n");
++ } else {
++ *duplex = HALF_DUPLEX;
++ DEBUGOUT("Half Duplex\n");
++ }
++
++ return E1000_SUCCESS;
++}
++
++/**
++ * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
++ * @hw: pointer to the HW structure
++ * @speed: stores the current speed
++ * @duplex: stores the current duplex
++ *
++ * Sets the speed and duplex to gigabit full duplex (the only possible option)
++ * for fiber/serdes links.
++ **/
++s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
++ u16 *speed, u16 *duplex)
++{
++ DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
++
++ *speed = SPEED_1000;
++ *duplex = FULL_DUPLEX;
++
++ return E1000_SUCCESS;
++}
++
++/**
++ * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
++ * @hw: pointer to the HW structure
++ *
++ * Acquire the HW semaphore to access the PHY or NVM
++ **/
++s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
++{
++ u32 swsm;
++ s32 ret_val = E1000_SUCCESS;
++ s32 timeout = hw->nvm.word_size + 1;
++ s32 i = 0;
++
++ DEBUGFUNC("e1000_get_hw_semaphore_generic");
++
++ /* Get the SW semaphore */
++ while (i < timeout) {
++ swsm = E1000_READ_REG(hw, E1000_SWSM);
++ if (!(swsm & E1000_SWSM_SMBI))
++ break;
++
++ usec_delay(50);
++ i++;
++ }
++
++ if (i == timeout) {
++ DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++ /* Get the FW semaphore. */
++ for (i = 0; i < timeout; i++) {
++ swsm = E1000_READ_REG(hw, E1000_SWSM);
++ E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
++
++ /* Semaphore acquired if bit latched */
++ if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
++ break;
++
++ usec_delay(50);
++ }
++
++ if (i == timeout) {
++ /* Release semaphores */
++ e1000_put_hw_semaphore_generic(hw);
++ DEBUGOUT("Driver can't access the NVM\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_put_hw_semaphore_generic - Release hardware semaphore
++ * @hw: pointer to the HW structure
++ *
++ * Release hardware semaphore used to access the PHY or NVM
++ **/
++void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
++{
++ u32 swsm;
++
++ DEBUGFUNC("e1000_put_hw_semaphore_generic");
++
++ swsm = E1000_READ_REG(hw, E1000_SWSM);
++
++ swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
++
++ E1000_WRITE_REG(hw, E1000_SWSM, swsm);
++}
++
++/**
++ * e1000_get_auto_rd_done_generic - Check for auto read completion
++ * @hw: pointer to the HW structure
++ *
++ * Check EEPROM for Auto Read done bit.
++ **/
++s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
++{
++ s32 i = 0;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_get_auto_rd_done_generic");
++
++ while (i < AUTO_READ_DONE_TIMEOUT) {
++ if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
++ break;
++ msec_delay(1);
++ i++;
++ }
++
++ if (i == AUTO_READ_DONE_TIMEOUT) {
++ DEBUGOUT("Auto read by HW from NVM has not completed.\n");
++ ret_val = -E1000_ERR_RESET;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_valid_led_default_generic - Verify a valid default LED config
++ * @hw: pointer to the HW structure
++ * @data: pointer to the NVM (EEPROM)
++ *
++ * Read the EEPROM for the current default LED configuration. If the
++ * LED configuration is not valid, set to a valid LED configuration.
++ **/
++s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
++{
++ s32 ret_val;
++
++ DEBUGFUNC("e1000_valid_led_default_generic");
++
++ ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++
++ if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
++ *data = ID_LED_DEFAULT;
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_id_led_init_generic -
++ * @hw: pointer to the HW structure
++ *
++ **/
++s32 e1000_id_led_init_generic(struct e1000_hw * hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++ s32 ret_val;
++ const u32 ledctl_mask = 0x000000FF;
++ const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
++ const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
++ u16 data, i, temp;
++ const u16 led_mask = 0x0F;
++
++ DEBUGFUNC("e1000_id_led_init_generic");
++
++ ret_val = hw->nvm.ops.valid_led_default(hw, &data);
++ if (ret_val)
++ goto out;
++
++ mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
++ mac->ledctl_mode1 = mac->ledctl_default;
++ mac->ledctl_mode2 = mac->ledctl_default;
++
++ for (i = 0; i < 4; i++) {
++ temp = (data >> (i << 2)) & led_mask;
++ switch (temp) {
++ case ID_LED_ON1_DEF2:
++ case ID_LED_ON1_ON2:
++ case ID_LED_ON1_OFF2:
++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
++ mac->ledctl_mode1 |= ledctl_on << (i << 3);
++ break;
++ case ID_LED_OFF1_DEF2:
++ case ID_LED_OFF1_ON2:
++ case ID_LED_OFF1_OFF2:
++ mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
++ mac->ledctl_mode1 |= ledctl_off << (i << 3);
++ break;
++ default:
++ /* Do nothing */
++ break;
++ }
++ switch (temp) {
++ case ID_LED_DEF1_ON2:
++ case ID_LED_ON1_ON2:
++ case ID_LED_OFF1_ON2:
++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
++ mac->ledctl_mode2 |= ledctl_on << (i << 3);
++ break;
++ case ID_LED_DEF1_OFF2:
++ case ID_LED_ON1_OFF2:
++ case ID_LED_OFF1_OFF2:
++ mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
++ mac->ledctl_mode2 |= ledctl_off << (i << 3);
++ break;
++ default:
++ /* Do nothing */
++ break;
++ }
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_setup_led_generic - Configures SW controllable LED
++ * @hw: pointer to the HW structure
++ *
++ * This prepares the SW controllable LED for use and saves the current state
++ * of the LED so it can be later restored.
++ **/
++s32 e1000_setup_led_generic(struct e1000_hw *hw)
++{
++ u32 ledctl;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_setup_led_generic");
++
++ if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
++ ret_val = -E1000_ERR_CONFIG;
++ goto out;
++ }
++
++ if (hw->phy.media_type == e1000_media_type_fiber) {
++ ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
++ hw->mac.ledctl_default = ledctl;
++ /* Turn off LED0 */
++ ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
++ E1000_LEDCTL_LED0_BLINK |
++ E1000_LEDCTL_LED0_MODE_MASK);
++ ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
++ E1000_LEDCTL_LED0_MODE_SHIFT);
++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
++ } else if (hw->phy.media_type == e1000_media_type_copper) {
++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_cleanup_led_generic - Set LED config to default operation
++ * @hw: pointer to the HW structure
++ *
++ * Remove the current LED configuration and set the LED configuration
++ * to the default value, saved from the EEPROM.
++ **/
++s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_cleanup_led_generic");
++
++ if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) {
++ ret_val = -E1000_ERR_CONFIG;
++ goto out;
++ }
++
++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_blink_led_generic - Blink LED
++ * @hw: pointer to the HW structure
++ *
++ * Blink the LEDs which are set to be on.
++ **/
++s32 e1000_blink_led_generic(struct e1000_hw *hw)
++{
++ u32 ledctl_blink = 0;
++ u32 i;
++
++ DEBUGFUNC("e1000_blink_led_generic");
++
++ if (hw->phy.media_type == e1000_media_type_fiber) {
++ /* always blink LED0 for PCI-E fiber */
++ ledctl_blink = E1000_LEDCTL_LED0_BLINK |
++ (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
++ } else {
++ /*
++ * set the blink bit for each LED that's "on" (0x0E)
++ * in ledctl_mode2
++ */
++ ledctl_blink = hw->mac.ledctl_mode2;
++ for (i = 0; i < 4; i++)
++ if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
++ E1000_LEDCTL_MODE_LED_ON)
++ ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
++ (i * 8));
++ }
++
++ E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
++
++ return E1000_SUCCESS;
++}
++
++/**
++ * e1000_led_on_generic - Turn LED on
++ * @hw: pointer to the HW structure
++ *
++ * Turn LED on.
++ **/
++s32 e1000_led_on_generic(struct e1000_hw *hw)
++{
++ u32 ctrl;
++
++ DEBUGFUNC("e1000_led_on_generic");
++
++ switch (hw->phy.media_type) {
++ case e1000_media_type_fiber:
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++ ctrl &= ~E1000_CTRL_SWDPIN0;
++ ctrl |= E1000_CTRL_SWDPIO0;
++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
++ break;
++ case e1000_media_type_copper:
++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
++ break;
++ default:
++ break;
++ }
++
++ return E1000_SUCCESS;
++}
++
++/**
++ * e1000_led_off_generic - Turn LED off
++ * @hw: pointer to the HW structure
++ *
++ * Turn LED off.
++ **/
++s32 e1000_led_off_generic(struct e1000_hw *hw)
++{
++ u32 ctrl;
++
++ DEBUGFUNC("e1000_led_off_generic");
++
++ switch (hw->phy.media_type) {
++ case e1000_media_type_fiber:
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++ ctrl |= E1000_CTRL_SWDPIN0;
++ ctrl |= E1000_CTRL_SWDPIO0;
++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
++ break;
++ case e1000_media_type_copper:
++ E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
++ break;
++ default:
++ break;
++ }
++
++ return E1000_SUCCESS;
++}
++
++/**
++ * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
++ * @hw: pointer to the HW structure
++ * @no_snoop: bitmap of snoop events
++ *
++ * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
++ **/
++void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
++{
++ u32 gcr;
++
++ DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
++
++ if (hw->bus.type != e1000_bus_type_pci_express)
++ goto out;
++
++ if (no_snoop) {
++ gcr = E1000_READ_REG(hw, E1000_GCR);
++ gcr &= ~(PCIE_NO_SNOOP_ALL);
++ gcr |= no_snoop;
++ E1000_WRITE_REG(hw, E1000_GCR, gcr);
++ }
++out:
++ return;
++}
++
++/**
++ * e1000_disable_pcie_master_generic - Disables PCI-express master access
++ * @hw: pointer to the HW structure
++ *
++ * Returns 0 (E1000_SUCCESS) if successful, else returns -10
++ * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
++ * the master requests to be disabled.
++ *
++ * Disables PCI-Express master access and verifies there are no pending
++ * requests.
++ **/
++s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
++{
++ u32 ctrl;
++ s32 timeout = MASTER_DISABLE_TIMEOUT;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_disable_pcie_master_generic");
++
++ if (hw->bus.type != e1000_bus_type_pci_express)
++ goto out;
++
++ ctrl = E1000_READ_REG(hw, E1000_CTRL);
++ ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
++ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
++
++ while (timeout) {
++ if (!(E1000_READ_REG(hw, E1000_STATUS) &
++ E1000_STATUS_GIO_MASTER_ENABLE))
++ break;
++ usec_delay(100);
++ timeout--;
++ }
++
++ if (!timeout) {
++ DEBUGOUT("Master requests are pending.\n");
++ ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
++ * @hw: pointer to the HW structure
++ *
++ * Reset the Adaptive Interframe Spacing throttle to default values.
++ **/
++void e1000_reset_adaptive_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++
++ DEBUGFUNC("e1000_reset_adaptive_generic");
++
++ if (!mac->adaptive_ifs) {
++ DEBUGOUT("Not in Adaptive IFS mode!\n");
++ goto out;
++ }
++
++ if (!mac->ifs_params_forced) {
++ mac->current_ifs_val = 0;
++ mac->ifs_min_val = IFS_MIN;
++ mac->ifs_max_val = IFS_MAX;
++ mac->ifs_step_size = IFS_STEP;
++ mac->ifs_ratio = IFS_RATIO;
++ }
++
++ mac->in_ifs_mode = false;
++ E1000_WRITE_REG(hw, E1000_AIT, 0);
++out:
++ return;
++}
++
++/**
++ * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
++ * @hw: pointer to the HW structure
++ *
++ * Update the Adaptive Interframe Spacing Throttle value based on the
++ * time between transmitted packets and time between collisions.
++ **/
++void e1000_update_adaptive_generic(struct e1000_hw *hw)
++{
++ struct e1000_mac_info *mac = &hw->mac;
++
++ DEBUGFUNC("e1000_update_adaptive_generic");
++
++ if (!mac->adaptive_ifs) {
++ DEBUGOUT("Not in Adaptive IFS mode!\n");
++ goto out;
++ }
++
++ if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
++ if (mac->tx_packet_delta > MIN_NUM_XMITS) {
++ mac->in_ifs_mode = true;
++ if (mac->current_ifs_val < mac->ifs_max_val) {
++ if (!mac->current_ifs_val)
++ mac->current_ifs_val = mac->ifs_min_val;
++ else
++ mac->current_ifs_val +=
++ mac->ifs_step_size;
++ E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
++ }
++ }
++ } else {
++ if (mac->in_ifs_mode &&
++ (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
++ mac->current_ifs_val = 0;
++ mac->in_ifs_mode = false;
++ E1000_WRITE_REG(hw, E1000_AIT, 0);
++ }
++ }
++out:
++ return;
++}
++
++/**
++ * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
++ * @hw: pointer to the HW structure
++ *
++ * Verify that when not using auto-negotiation that MDI/MDIx is correctly
++ * set, which is forced to MDI mode only.
++ **/
++s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_validate_mdi_setting_generic");
++
++ if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
++ DEBUGOUT("Invalid MDI setting detected\n");
++ hw->phy.mdix = 1;
++ ret_val = -E1000_ERR_CONFIG;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
++ * @hw: pointer to the HW structure
++ * @reg: 32bit register offset such as E1000_SCTL
++ * @offset: register offset to write to
++ * @data: data to write at register offset
++ *
++ * Writes an address/data control type register. There are several of these
++ * and they all have the format address << 8 | data and bit 31 is polled for
++ * completion.
++ **/
++s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
++ u32 offset, u8 data)
++{
++ u32 i, regvalue = 0;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
++
++ /* Set up the address and data */
++ regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
++ E1000_WRITE_REG(hw, reg, regvalue);
++
++ /* Poll the ready bit to see if the MDI read completed */
++ for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
++ usec_delay(5);
++ regvalue = E1000_READ_REG(hw, reg);
++ if (regvalue & E1000_GEN_CTL_READY)
++ break;
++ }
++ if (!(regvalue & E1000_GEN_CTL_READY)) {
++ DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
++ ret_val = -E1000_ERR_PHY;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_mac.h linux-2.6.22-10/drivers/net/e1000e/e1000_mac.h
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_mac.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_mac.h 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,86 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++#ifndef _E1000_MAC_H_
++#define _E1000_MAC_H_
++
++/*
++ * Functions that should not be called directly from drivers but can be used
++ * by other files in this 'shared code'
++ */
++void e1000_init_mac_ops_generic(struct e1000_hw *hw);
++s32 e1000_blink_led_generic(struct e1000_hw *hw);
++s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw);
++s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw);
++s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw);
++s32 e1000_cleanup_led_generic(struct e1000_hw *hw);
++s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw);
++s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw);
++s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw);
++s32 e1000_force_mac_fc_generic(struct e1000_hw *hw);
++s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw);
++s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw);
++s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw);
++s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
++ u16 *duplex);
++s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
++ u16 *speed, u16 *duplex);
++s32 e1000_id_led_init_generic(struct e1000_hw *hw);
++s32 e1000_led_on_generic(struct e1000_hw *hw);
++s32 e1000_led_off_generic(struct e1000_hw *hw);
++void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
++ u8 *mc_addr_list, u32 mc_addr_count,
++ u32 rar_used_count, u32 rar_count);
++s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw);
++s32 e1000_set_default_fc_generic(struct e1000_hw *hw);
++s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw);
++s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw);
++s32 e1000_setup_led_generic(struct e1000_hw *hw);
++s32 e1000_setup_link_generic(struct e1000_hw *hw);
++s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
++s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
++ u32 offset, u8 data);
++
++u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);
++
++void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw);
++void e1000_clear_vfta_generic(struct e1000_hw *hw);
++void e1000_config_collision_dist_generic(struct e1000_hw *hw);
++void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);
++void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
++void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
++void e1000_put_hw_semaphore_generic(struct e1000_hw *hw);
++void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
++s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
++void e1000_remove_device_generic(struct e1000_hw *hw);
++void e1000_reset_adaptive_generic(struct e1000_hw *hw);
++void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);
++void e1000_update_adaptive_generic(struct e1000_hw *hw);
++void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
++
++#endif
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_manage.c linux-2.6.22-10/drivers/net/e1000e/e1000_manage.c
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_manage.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_manage.c 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,383 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++#include "e1000_hw.h"
++
++static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
++
++/**
++ * e1000_calculate_checksum - Calculate checksum for buffer
++ * @buffer: pointer to EEPROM
++ * @length: size of EEPROM to calculate a checksum for
++ *
++ * Calculates the checksum for some buffer on a specified length. The
++ * checksum calculated is returned.
++ **/
++static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
++{
++ u32 i;
++ u8 sum = 0;
++
++ DEBUGFUNC("e1000_calculate_checksum");
++
++ if (!buffer)
++ return 0;
++
++ for (i = 0; i < length; i++)
++ sum += buffer[i];
++
++ return (u8) (0 - sum);
++}
++
++/**
++ * e1000_mng_enable_host_if_generic - Checks host interface is enabled
++ * @hw: pointer to the HW structure
++ *
++ * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
++ *
++ * This function checks whether the HOST IF is enabled for command operation
++ * and also checks whether the previous command is completed. It busy waits
++ * in case of previous command is not completed.
++ **/
++s32 e1000_mng_enable_host_if_generic(struct e1000_hw * hw)
++{
++ u32 hicr;
++ s32 ret_val = E1000_SUCCESS;
++ u8 i;
++
++ DEBUGFUNC("e1000_mng_enable_host_if_generic");
++
++ /* Check that the host interface is enabled. */
++ hicr = E1000_READ_REG(hw, E1000_HICR);
++ if ((hicr & E1000_HICR_EN) == 0) {
++ DEBUGOUT("E1000_HOST_EN bit disabled.\n");
++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
++ goto out;
++ }
++ /* check the previous command is completed */
++ for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
++ hicr = E1000_READ_REG(hw, E1000_HICR);
++ if (!(hicr & E1000_HICR_C))
++ break;
++ msec_delay_irq(1);
++ }
++
++ if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
++ DEBUGOUT("Previous command timeout failed .\n");
++ ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_check_mng_mode_generic - Generic check management mode
++ * @hw: pointer to the HW structure
++ *
++ * Reads the firmware semaphore register and returns true (>0) if
++ * manageability is enabled, else false (0).
++ **/
++bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
++{
++ u32 fwsm;
++
++ DEBUGFUNC("e1000_check_mng_mode_generic");
++
++ fwsm = E1000_READ_REG(hw, E1000_FWSM);
++
++ return ((fwsm & E1000_FWSM_MODE_MASK) ==
++ (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
++}
++
++/**
++ * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
++ * @hw: pointer to the HW structure
++ *
++ * Enables packet filtering on transmit packets if manageability is enabled
++ * and host interface is enabled.
++ **/
++bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
++{
++ struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
++ u32 *buffer = (u32 *)&hw->mng_cookie;
++ u32 offset;
++ s32 ret_val, hdr_csum, csum;
++ u8 i, len;
++ bool tx_filter = true;
++
++ DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
++
++ /* No manageability, no filtering */
++ if (!hw->mac.ops.check_mng_mode(hw)) {
++ tx_filter = false;
++ goto out;
++ }
++
++ /*
++ * If we can't read from the host interface for whatever
++ * reason, disable filtering.
++ */
++ ret_val = hw->mac.ops.mng_enable_host_if(hw);
++ if (ret_val != E1000_SUCCESS) {
++ tx_filter = false;
++ goto out;
++ }
++
++ /* Read in the header. Length and offset are in dwords. */
++ len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
++ offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
++ for (i = 0; i < len; i++) {
++ *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
++ E1000_HOST_IF,
++ offset + i);
++ }
++ hdr_csum = hdr->checksum;
++ hdr->checksum = 0;
++ csum = e1000_calculate_checksum((u8 *)hdr,
++ E1000_MNG_DHCP_COOKIE_LENGTH);
++ /*
++ * If either the checksums or signature don't match, then
++ * the cookie area isn't considered valid, in which case we
++ * take the safe route of assuming Tx filtering is enabled.
++ */
++ if (hdr_csum != csum)
++ goto out;
++ if (hdr->signature != E1000_IAMT_SIGNATURE)
++ goto out;
++
++ /* Cookie area is valid, make the final check for filtering. */
++ if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
++ tx_filter = false;
++
++out:
++ hw->mac.tx_pkt_filtering = tx_filter;
++ return tx_filter;
++}
++
++/**
++ * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
++ * @hw: pointer to the HW structure
++ * @buffer: pointer to the host interface
++ * @length: size of the buffer
++ *
++ * Writes the DHCP information to the host interface.
++ **/
++s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw * hw, u8 *buffer,
++ u16 length)
++{
++ struct e1000_host_mng_command_header hdr;
++ s32 ret_val;
++ u32 hicr;
++
++ DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
++
++ hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
++ hdr.command_length = length;
++ hdr.reserved1 = 0;
++ hdr.reserved2 = 0;
++ hdr.checksum = 0;
++
++ /* Enable the host interface */
++ ret_val = hw->mac.ops.mng_enable_host_if(hw);
++ if (ret_val)
++ goto out;
++
++ /* Populate the host interface with the contents of "buffer". */
++ ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
++ sizeof(hdr), &(hdr.checksum));
++ if (ret_val)
++ goto out;
++
++ /* Write the manageability command header */
++ ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
++ if (ret_val)
++ goto out;
++
++ /* Tell the ARC a new command is pending. */
++ hicr = E1000_READ_REG(hw, E1000_HICR);
++ E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_mng_write_cmd_header_generic - Writes manageability command header
++ * @hw: pointer to the HW structure
++ * @hdr: pointer to the host interface command header
++ *
++ * Writes the command header after does the checksum calculation.
++ **/
++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw * hw,
++ struct e1000_host_mng_command_header * hdr)
++{
++ u16 i, length = sizeof(struct e1000_host_mng_command_header);
++
++ DEBUGFUNC("e1000_mng_write_cmd_header_generic");
++
++ /* Write the whole command header structure with new checksum. */
++
++ hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
++
++ length >>= 2;
++ /* Write the relevant command block into the ram area. */
++ for (i = 0; i < length; i++) {
++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
++ *((u32 *) hdr + i));
++ E1000_WRITE_FLUSH(hw);
++ }
++
++ return E1000_SUCCESS;
++}
++
++/**
++ * e1000_mng_host_if_write_generic - Write to the manageability host interface
++ * @hw: pointer to the HW structure
++ * @buffer: pointer to the host interface buffer
++ * @length: size of the buffer
++ * @offset: location in the buffer to write to
++ * @sum: sum of the data (not checksum)
++ *
++ * This function writes the buffer content at the offset given on the host if.
++ * It also does alignment considerations to do the writes in most efficient
++ * way. Also fills up the sum of the buffer in *buffer parameter.
++ **/
++s32 e1000_mng_host_if_write_generic(struct e1000_hw * hw, u8 *buffer,
++ u16 length, u16 offset, u8 *sum)
++{
++ u8 *tmp;
++ u8 *bufptr = buffer;
++ u32 data = 0;
++ s32 ret_val = E1000_SUCCESS;
++ u16 remaining, i, j, prev_bytes;
++
++ DEBUGFUNC("e1000_mng_host_if_write_generic");
++
++ /* sum = only sum of the data and it is not checksum */
++
++ if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
++ ret_val = -E1000_ERR_PARAM;
++ goto out;
++ }
++
++ tmp = (u8 *)&data;
++ prev_bytes = offset & 0x3;
++ offset >>= 2;
++
++ if (prev_bytes) {
++ data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
++ for (j = prev_bytes; j < sizeof(u32); j++) {
++ *(tmp + j) = *bufptr++;
++ *sum += *(tmp + j);
++ }
++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
++ length -= j - prev_bytes;
++ offset++;
++ }
++
++ remaining = length & 0x3;
++ length -= remaining;
++
++ /* Calculate length in DWORDs */
++ length >>= 2;
++
++ /*
++ * The device driver writes the relevant command block into the
++ * ram area.
++ */
++ for (i = 0; i < length; i++) {
++ for (j = 0; j < sizeof(u32); j++) {
++ *(tmp + j) = *bufptr++;
++ *sum += *(tmp + j);
++ }
++
++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
++ }
++ if (remaining) {
++ for (j = 0; j < sizeof(u32); j++) {
++ if (j < remaining)
++ *(tmp + j) = *bufptr++;
++ else
++ *(tmp + j) = 0;
++
++ *sum += *(tmp + j);
++ }
++ E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_enable_mng_pass_thru - Enable processing of ARP's
++ * @hw: pointer to the HW structure
++ *
++ * Verifies the hardware needs to allow ARPs to be processed by the host.
++ **/
++bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
++{
++ u32 manc;
++ u32 fwsm, factps;
++ bool ret_val = false;
++
++ DEBUGFUNC("e1000_enable_mng_pass_thru");
++
++ if (!hw->mac.asf_firmware_present)
++ goto out;
++
++ manc = E1000_READ_REG(hw, E1000_MANC);
++
++ if (!(manc & E1000_MANC_RCV_TCO_EN) ||
++ !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
++ goto out;
++
++ if (hw->mac.arc_subsystem_valid) {
++ fwsm = E1000_READ_REG(hw, E1000_FWSM);
++ factps = E1000_READ_REG(hw, E1000_FACTPS);
++
++ if (!(factps & E1000_FACTPS_MNGCG) &&
++ ((fwsm & E1000_FWSM_MODE_MASK) ==
++ (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
++ ret_val = true;
++ goto out;
++ }
++ } else {
++ if ((manc & E1000_MANC_SMBUS_EN) &&
++ !(manc & E1000_MANC_ASF_EN)) {
++ ret_val = true;
++ goto out;
++ }
++ }
++
++out:
++ return ret_val;
++}
++
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_manage.h linux-2.6.22-10/drivers/net/e1000e/e1000_manage.h
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_manage.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_manage.h 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,82 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++#ifndef _E1000_MANAGE_H_
++#define _E1000_MANAGE_H_
++
++bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
++bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
++s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
++s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
++ u16 length, u16 offset, u8 *sum);
++s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
++ struct e1000_host_mng_command_header *hdr);
++s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
++ u8 *buffer, u16 length);
++bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
++
++typedef enum {
++ e1000_mng_mode_none = 0,
++ e1000_mng_mode_asf,
++ e1000_mng_mode_pt,
++ e1000_mng_mode_ipmi,
++ e1000_mng_mode_host_if_only
++} e1000_mng_mode;
++
++#define E1000_FACTPS_MNGCG 0x20000000
++
++#define E1000_FWSM_MODE_MASK 0xE
++#define E1000_FWSM_MODE_SHIFT 1
++
++#define E1000_MNG_IAMT_MODE 0x3
++#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
++#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
++#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
++#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
++#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
++#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
++
++#define E1000_VFTA_ENTRY_SHIFT 5
++#define E1000_VFTA_ENTRY_MASK 0x7F
++#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
++
++#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
++#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
++#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
++
++#define E1000_HICR_EN 0x01 /* Enable bit - RO */
++/* Driver sets this bit when done to put command in RAM */
++#define E1000_HICR_C 0x02
++#define E1000_HICR_SV 0x04 /* Status Validity */
++#define E1000_HICR_FW_RESET_ENABLE 0x40
++#define E1000_HICR_FW_RESET 0x80
++
++/* Intel(R) Active Management Technology signature */
++#define E1000_IAMT_SIGNATURE 0x544D4149
++
++#endif
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.c linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.c
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.c 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,875 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++#include "e1000_hw.h"
++
++/**
++ * e1000_init_nvm_ops_generic - Initialize NVM function pointers
++ * @hw: pointer to the HW structure
++ *
++ * Setups up the function pointers to no-op functions
++ **/
++void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ DEBUGFUNC("e1000_init_nvm_ops_generic");
++
++ /* Initialize function pointers */
++ nvm->ops.reload = e1000_reload_nvm_generic;
++}
++
++/**
++ * e1000_raise_eec_clk - Raise EEPROM clock
++ * @hw: pointer to the HW structure
++ * @eecd: pointer to the EEPROM
++ *
++ * Enable/Raise the EEPROM clock bit.
++ **/
++static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
++{
++ *eecd = *eecd | E1000_EECD_SK;
++ E1000_WRITE_REG(hw, E1000_EECD, *eecd);
++ E1000_WRITE_FLUSH(hw);
++ usec_delay(hw->nvm.delay_usec);
++}
++
++/**
++ * e1000_lower_eec_clk - Lower EEPROM clock
++ * @hw: pointer to the HW structure
++ * @eecd: pointer to the EEPROM
++ *
++ * Clear/Lower the EEPROM clock bit.
++ **/
++static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
++{
++ *eecd = *eecd & ~E1000_EECD_SK;
++ E1000_WRITE_REG(hw, E1000_EECD, *eecd);
++ E1000_WRITE_FLUSH(hw);
++ usec_delay(hw->nvm.delay_usec);
++}
++
++/**
++ * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
++ * @hw: pointer to the HW structure
++ * @data: data to send to the EEPROM
++ * @count: number of bits to shift out
++ *
++ * We need to shift 'count' bits out to the EEPROM. So, the value in the
++ * "data" parameter will be shifted out to the EEPROM one bit at a time.
++ * In order to do this, "data" must be broken down into bits.
++ **/
++static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ u32 eecd = E1000_READ_REG(hw, E1000_EECD);
++ u32 mask;
++
++ DEBUGFUNC("e1000_shift_out_eec_bits");
++
++ mask = 0x01 << (count - 1);
++ if (nvm->type == e1000_nvm_eeprom_microwire)
++ eecd &= ~E1000_EECD_DO;
++ else if (nvm->type == e1000_nvm_eeprom_spi)
++ eecd |= E1000_EECD_DO;
++
++ do {
++ eecd &= ~E1000_EECD_DI;
++
++ if (data & mask)
++ eecd |= E1000_EECD_DI;
++
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++
++ usec_delay(nvm->delay_usec);
++
++ e1000_raise_eec_clk(hw, &eecd);
++ e1000_lower_eec_clk(hw, &eecd);
++
++ mask >>= 1;
++ } while (mask);
++
++ eecd &= ~E1000_EECD_DI;
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++}
++
++/**
++ * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
++ * @hw: pointer to the HW structure
++ * @count: number of bits to shift in
++ *
++ * In order to read a register from the EEPROM, we need to shift 'count' bits
++ * in from the EEPROM. Bits are "shifted in" by raising the clock input to
++ * the EEPROM (setting the SK bit), and then reading the value of the data out
++ * "DO" bit. During this "shifting in" process the data in "DI" bit should
++ * always be clear.
++ **/
++static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
++{
++ u32 eecd;
++ u32 i;
++ u16 data;
++
++ DEBUGFUNC("e1000_shift_in_eec_bits");
++
++ eecd = E1000_READ_REG(hw, E1000_EECD);
++
++ eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
++ data = 0;
++
++ for (i = 0; i < count; i++) {
++ data <<= 1;
++ e1000_raise_eec_clk(hw, &eecd);
++
++ eecd = E1000_READ_REG(hw, E1000_EECD);
++
++ eecd &= ~E1000_EECD_DI;
++ if (eecd & E1000_EECD_DO)
++ data |= 1;
++
++ e1000_lower_eec_clk(hw, &eecd);
++ }
++
++ return data;
++}
++
++/**
++ * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
++ * @hw: pointer to the HW structure
++ * @ee_reg: EEPROM flag for polling
++ *
++ * Polls the EEPROM status bit for either read or write completion based
++ * upon the value of 'ee_reg'.
++ **/
++s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
++{
++ u32 attempts = 100000;
++ u32 i, reg = 0;
++ s32 ret_val = -E1000_ERR_NVM;
++
++ DEBUGFUNC("e1000_poll_eerd_eewr_done");
++
++ for (i = 0; i < attempts; i++) {
++ if (ee_reg == E1000_NVM_POLL_READ)
++ reg = E1000_READ_REG(hw, E1000_EERD);
++ else
++ reg = E1000_READ_REG(hw, E1000_EEWR);
++
++ if (reg & E1000_NVM_RW_REG_DONE) {
++ ret_val = E1000_SUCCESS;
++ break;
++ }
++
++ usec_delay(5);
++ }
++
++ return ret_val;
++}
++
++/**
++ * e1000_acquire_nvm_generic - Generic request for access to EEPROM
++ * @hw: pointer to the HW structure
++ *
++ * Set the EEPROM access request bit and wait for EEPROM access grant bit.
++ * Return successful if access grant bit set, else clear the request for
++ * EEPROM access and return -E1000_ERR_NVM (-1).
++ **/
++s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
++{
++ u32 eecd = E1000_READ_REG(hw, E1000_EECD);
++ s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_acquire_nvm_generic");
++
++ E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
++ eecd = E1000_READ_REG(hw, E1000_EECD);
++
++ while (timeout) {
++ if (eecd & E1000_EECD_GNT)
++ break;
++ usec_delay(5);
++ eecd = E1000_READ_REG(hw, E1000_EECD);
++ timeout--;
++ }
++
++ if (!timeout) {
++ eecd &= ~E1000_EECD_REQ;
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ DEBUGOUT("Could not acquire NVM grant\n");
++ ret_val = -E1000_ERR_NVM;
++ }
++
++ return ret_val;
++}
++
++/**
++ * e1000_standby_nvm - Return EEPROM to standby state
++ * @hw: pointer to the HW structure
++ *
++ * Return the EEPROM to a standby state.
++ **/
++static void e1000_standby_nvm(struct e1000_hw *hw)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ u32 eecd = E1000_READ_REG(hw, E1000_EECD);
++
++ DEBUGFUNC("e1000_standby_nvm");
++
++ if (nvm->type == e1000_nvm_eeprom_microwire) {
++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ usec_delay(nvm->delay_usec);
++
++ e1000_raise_eec_clk(hw, &eecd);
++
++ /* Select EEPROM */
++ eecd |= E1000_EECD_CS;
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ usec_delay(nvm->delay_usec);
++
++ e1000_lower_eec_clk(hw, &eecd);
++ } else if (nvm->type == e1000_nvm_eeprom_spi) {
++ /* Toggle CS to flush commands */
++ eecd |= E1000_EECD_CS;
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ usec_delay(nvm->delay_usec);
++ eecd &= ~E1000_EECD_CS;
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ E1000_WRITE_FLUSH(hw);
++ usec_delay(nvm->delay_usec);
++ }
++}
++
++/**
++ * e1000_stop_nvm - Terminate EEPROM command
++ * @hw: pointer to the HW structure
++ *
++ * Terminates the current command by inverting the EEPROM's chip select pin.
++ **/
++void e1000_stop_nvm(struct e1000_hw *hw)
++{
++ u32 eecd;
++
++ DEBUGFUNC("e1000_stop_nvm");
++
++ eecd = E1000_READ_REG(hw, E1000_EECD);
++ if (hw->nvm.type == e1000_nvm_eeprom_spi) {
++ /* Pull CS high */
++ eecd |= E1000_EECD_CS;
++ e1000_lower_eec_clk(hw, &eecd);
++ } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
++ /* CS on Microwire is active-high */
++ eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ e1000_raise_eec_clk(hw, &eecd);
++ e1000_lower_eec_clk(hw, &eecd);
++ }
++}
++
++/**
++ * e1000_release_nvm_generic - Release exclusive access to EEPROM
++ * @hw: pointer to the HW structure
++ *
++ * Stop any current commands to the EEPROM and clear the EEPROM request bit.
++ **/
++void e1000_release_nvm_generic(struct e1000_hw *hw)
++{
++ u32 eecd;
++
++ DEBUGFUNC("e1000_release_nvm_generic");
++
++ e1000_stop_nvm(hw);
++
++ eecd = E1000_READ_REG(hw, E1000_EECD);
++ eecd &= ~E1000_EECD_REQ;
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++}
++
++/**
++ * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
++ * @hw: pointer to the HW structure
++ *
++ * Setups the EEPROM for reading and writing.
++ **/
++static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ u32 eecd = E1000_READ_REG(hw, E1000_EECD);
++ s32 ret_val = E1000_SUCCESS;
++ u16 timeout = 0;
++ u8 spi_stat_reg;
++
++ DEBUGFUNC("e1000_ready_nvm_eeprom");
++
++ if (nvm->type == e1000_nvm_eeprom_microwire) {
++ /* Clear SK and DI */
++ eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ /* Set CS */
++ eecd |= E1000_EECD_CS;
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ } else if (nvm->type == e1000_nvm_eeprom_spi) {
++ /* Clear SK and CS */
++ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
++ E1000_WRITE_REG(hw, E1000_EECD, eecd);
++ usec_delay(1);
++ timeout = NVM_MAX_RETRY_SPI;
++
++ /*
++ * Read "Status Register" repeatedly until the LSB is cleared.
++ * The EEPROM will signal that the command has been completed
++ * by clearing bit 0 of the internal status register. If it's
++ * not cleared within 'timeout', then error out.
++ */
++ while (timeout) {
++ e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
++ hw->nvm.opcode_bits);
++ spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
++ if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
++ break;
++
++ usec_delay(5);
++ e1000_standby_nvm(hw);
++ timeout--;
++ }
++
++ if (!timeout) {
++ DEBUGOUT("SPI NVM Status error\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_nvm_spi - Read EEPROM's using SPI
++ * @hw: pointer to the HW structure
++ * @offset: offset of word in the EEPROM to read
++ * @words: number of words to read
++ * @data: word read from the EEPROM
++ *
++ * Reads a 16 bit word from the EEPROM.
++ **/
++s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ u32 i = 0;
++ s32 ret_val;
++ u16 word_in;
++ u8 read_opcode = NVM_READ_OPCODE_SPI;
++
++ DEBUGFUNC("e1000_read_nvm_spi");
++
++ /*
++ * A check for invalid values: offset too large, too many words,
++ * and not enough words.
++ */
++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
++ (words == 0)) {
++ DEBUGOUT("nvm parameter(s) out of bounds\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++ ret_val = nvm->ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ ret_val = e1000_ready_nvm_eeprom(hw);
++ if (ret_val)
++ goto release;
++
++ e1000_standby_nvm(hw);
++
++ if ((nvm->address_bits == 8) && (offset >= 128))
++ read_opcode |= NVM_A8_OPCODE_SPI;
++
++ /* Send the READ command (opcode + addr) */
++ e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
++ e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
++
++ /*
++ * Read the data. SPI NVMs increment the address with each byte
++ * read and will roll over if reading beyond the end. This allows
++ * us to read the whole NVM from any offset
++ */
++ for (i = 0; i < words; i++) {
++ word_in = e1000_shift_in_eec_bits(hw, 16);
++ data[i] = (word_in >> 8) | (word_in << 8);
++ }
++
++release:
++ nvm->ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_nvm_microwire - Reads EEPROM's using microwire
++ * @hw: pointer to the HW structure
++ * @offset: offset of word in the EEPROM to read
++ * @words: number of words to read
++ * @data: word read from the EEPROM
++ *
++ * Reads a 16 bit word from the EEPROM.
++ **/
++s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
++ u16 *data)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ u32 i = 0;
++ s32 ret_val;
++ u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
++
++ DEBUGFUNC("e1000_read_nvm_microwire");
++
++ /*
++ * A check for invalid values: offset too large, too many words,
++ * and not enough words.
++ */
++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
++ (words == 0)) {
++ DEBUGOUT("nvm parameter(s) out of bounds\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++ ret_val = nvm->ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ ret_val = e1000_ready_nvm_eeprom(hw);
++ if (ret_val)
++ goto release;
++
++ for (i = 0; i < words; i++) {
++ /* Send the READ command (opcode + addr) */
++ e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
++ e1000_shift_out_eec_bits(hw, (u16)(offset + i),
++ nvm->address_bits);
++
++ /*
++ * Read the data. For microwire, each word requires the
++ * overhead of setup and tear-down.
++ */
++ data[i] = e1000_shift_in_eec_bits(hw, 16);
++ e1000_standby_nvm(hw);
++ }
++
++release:
++ nvm->ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_nvm_eerd - Reads EEPROM using EERD register
++ * @hw: pointer to the HW structure
++ * @offset: offset of word in the EEPROM to read
++ * @words: number of words to read
++ * @data: word read from the EEPROM
++ *
++ * Reads a 16 bit word from the EEPROM using the EERD register.
++ **/
++s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ u32 i, eerd = 0;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_read_nvm_eerd");
++
++ /*
++ * A check for invalid values: offset too large, too many words,
++ * too many words for the offset, and not enough words.
++ */
++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
++ (words == 0)) {
++ DEBUGOUT("nvm parameter(s) out of bounds\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++ for (i = 0; i < words; i++) {
++ eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
++ E1000_NVM_RW_REG_START;
++
++ E1000_WRITE_REG(hw, E1000_EERD, eerd);
++ ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
++ if (ret_val)
++ break;
++
++ data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
++ E1000_NVM_RW_REG_DATA);
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_write_nvm_spi - Write to EEPROM using SPI
++ * @hw: pointer to the HW structure
++ * @offset: offset within the EEPROM to be written to
++ * @words: number of words to write
++ * @data: 16 bit word(s) to be written to the EEPROM
++ *
++ * Writes data to EEPROM at offset using SPI interface.
++ *
++ * If e1000_update_nvm_checksum is not called after this function , the
++ * EEPROM will most likely contain an invalid checksum.
++ **/
++s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ s32 ret_val;
++ u16 widx = 0;
++
++ DEBUGFUNC("e1000_write_nvm_spi");
++
++ /*
++ * A check for invalid values: offset too large, too many words,
++ * and not enough words.
++ */
++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
++ (words == 0)) {
++ DEBUGOUT("nvm parameter(s) out of bounds\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++ ret_val = nvm->ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ while (widx < words) {
++ u8 write_opcode = NVM_WRITE_OPCODE_SPI;
++
++ ret_val = e1000_ready_nvm_eeprom(hw);
++ if (ret_val)
++ goto release;
++
++ e1000_standby_nvm(hw);
++
++ /* Send the WRITE ENABLE command (8 bit opcode) */
++ e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
++ nvm->opcode_bits);
++
++ e1000_standby_nvm(hw);
++
++ /*
++ * Some SPI eeproms use the 8th address bit embedded in the
++ * opcode
++ */
++ if ((nvm->address_bits == 8) && (offset >= 128))
++ write_opcode |= NVM_A8_OPCODE_SPI;
++
++ /* Send the Write command (8-bit opcode + addr) */
++ e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
++ e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
++ nvm->address_bits);
++
++ /* Loop to allow for up to whole page write of eeprom */
++ while (widx < words) {
++ u16 word_out = data[widx];
++ word_out = (word_out >> 8) | (word_out << 8);
++ e1000_shift_out_eec_bits(hw, word_out, 16);
++ widx++;
++
++ if ((((offset + widx) * 2) % nvm->page_size) == 0) {
++ e1000_standby_nvm(hw);
++ break;
++ }
++ }
++ }
++
++ msec_delay(nvm->semaphore_delay);
++release:
++ nvm->ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_write_nvm_microwire - Writes EEPROM using microwire
++ * @hw: pointer to the HW structure
++ * @offset: offset within the EEPROM to be written to
++ * @words: number of words to write
++ * @data: 16 bit word(s) to be written to the EEPROM
++ *
++ * Writes data to EEPROM at offset using microwire interface.
++ *
++ * If e1000_update_nvm_checksum is not called after this function , the
++ * EEPROM will most likely contain an invalid checksum.
++ **/
++s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
++ u16 *data)
++{
++ struct e1000_nvm_info *nvm = &hw->nvm;
++ s32 ret_val;
++ u32 eecd;
++ u16 words_written = 0;
++ u16 widx = 0;
++
++ DEBUGFUNC("e1000_write_nvm_microwire");
++
++ /*
++ * A check for invalid values: offset too large, too many words,
++ * and not enough words.
++ */
++ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
++ (words == 0)) {
++ DEBUGOUT("nvm parameter(s) out of bounds\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++ ret_val = nvm->ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ ret_val = e1000_ready_nvm_eeprom(hw);
++ if (ret_val)
++ goto release;
++
++ e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
++ (u16)(nvm->opcode_bits + 2));
++
++ e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
++
++ e1000_standby_nvm(hw);
++
++ while (words_written < words) {
++ e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
++ nvm->opcode_bits);
++
++ e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
++ nvm->address_bits);
++
++ e1000_shift_out_eec_bits(hw, data[words_written], 16);
++
++ e1000_standby_nvm(hw);
++
++ for (widx = 0; widx < 200; widx++) {
++ eecd = E1000_READ_REG(hw, E1000_EECD);
++ if (eecd & E1000_EECD_DO)
++ break;
++ usec_delay(50);
++ }
++
++ if (widx == 200) {
++ DEBUGOUT("NVM Write did not complete\n");
++ ret_val = -E1000_ERR_NVM;
++ goto release;
++ }
++
++ e1000_standby_nvm(hw);
++
++ words_written++;
++ }
++
++ e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
++ (u16)(nvm->opcode_bits + 2));
++
++ e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
++
++release:
++ nvm->ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_pba_num_generic - Read device part number
++ * @hw: pointer to the HW structure
++ * @pba_num: pointer to device part number
++ *
++ * Reads the product board assembly (PBA) number from the EEPROM and stores
++ * the value in pba_num.
++ **/
++s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
++{
++ s32 ret_val;
++ u16 nvm_data;
++
++ DEBUGFUNC("e1000_read_pba_num_generic");
++
++ ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++ *pba_num = (u32)(nvm_data << 16);
++
++ ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++ *pba_num |= nvm_data;
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_mac_addr_generic - Read device MAC address
++ * @hw: pointer to the HW structure
++ *
++ * Reads the device MAC address from the EEPROM and stores the value.
++ * Since devices with two ports use the same EEPROM, we increment the
++ * last bit in the MAC address for the second port.
++ **/
++s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++ u16 offset, nvm_data, i;
++
++ DEBUGFUNC("e1000_read_mac_addr");
++
++ for (i = 0; i < ETH_ADDR_LEN; i += 2) {
++ offset = i >> 1;
++ ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++ hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
++ hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
++ }
++
++ /* Flip last bit of mac address if we're on second port */
++ if (hw->bus.func == E1000_FUNC_1)
++ hw->mac.perm_addr[5] ^= 1;
++
++ for (i = 0; i < ETH_ADDR_LEN; i++)
++ hw->mac.addr[i] = hw->mac.perm_addr[i];
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
++ * @hw: pointer to the HW structure
++ *
++ * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
++ * and then verifies that the sum of the EEPROM is equal to 0xBABA.
++ **/
++s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++ u16 checksum = 0;
++ u16 i, nvm_data;
++
++ DEBUGFUNC("e1000_validate_nvm_checksum_generic");
++
++ for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
++ ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error\n");
++ goto out;
++ }
++ checksum += nvm_data;
++ }
++
++ if (checksum != (u16) NVM_SUM) {
++ DEBUGOUT("NVM Checksum Invalid\n");
++ ret_val = -E1000_ERR_NVM;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_update_nvm_checksum_generic - Update EEPROM checksum
++ * @hw: pointer to the HW structure
++ *
++ * Updates the EEPROM checksum by reading/adding each word of the EEPROM
++ * up to the checksum. Then calculates the EEPROM checksum and writes the
++ * value to the EEPROM.
++ **/
++s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
++{
++ s32 ret_val;
++ u16 checksum = 0;
++ u16 i, nvm_data;
++
++ DEBUGFUNC("e1000_update_nvm_checksum");
++
++ for (i = 0; i < NVM_CHECKSUM_REG; i++) {
++ ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
++ if (ret_val) {
++ DEBUGOUT("NVM Read Error while updating checksum.\n");
++ goto out;
++ }
++ checksum += nvm_data;
++ }
++ checksum = (u16) NVM_SUM - checksum;
++ ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
++ if (ret_val) {
++ DEBUGOUT("NVM Write Error while updating checksum.\n");
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_reload_nvm_generic - Reloads EEPROM
++ * @hw: pointer to the HW structure
++ *
++ * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
++ * extended control register.
++ **/
++void e1000_reload_nvm_generic(struct e1000_hw *hw)
++{
++ u32 ctrl_ext;
++
++ DEBUGFUNC("e1000_reload_nvm_generic");
++
++ usec_delay(10);
++ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
++ ctrl_ext |= E1000_CTRL_EXT_EE_RST;
++ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
++ E1000_WRITE_FLUSH(hw);
++}
++
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.h linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.h
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_nvm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_nvm.h 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,58 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++#ifndef _E1000_NVM_H_
++#define _E1000_NVM_H_
++
++void e1000_init_nvm_ops_generic(struct e1000_hw *hw);
++s32 e1000_acquire_nvm_generic(struct e1000_hw *hw);
++
++s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
++s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
++s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
++s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
++s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset,
++ u16 words, u16 *data);
++s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
++ u16 *data);
++s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
++s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw);
++s32 e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
++ u16 words, u16 *data);
++s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset,
++ u16 words, u16 *data);
++s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
++ u16 *data);
++s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw);
++void e1000_stop_nvm(struct e1000_hw *hw);
++void e1000_release_nvm_generic(struct e1000_hw *hw);
++void e1000_reload_nvm_generic(struct e1000_hw *hw);
++
++#define E1000_STM_OPCODE 0xDB00
++
++#endif
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_osdep.h linux-2.6.22-10/drivers/net/e1000e/e1000_osdep.h
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_osdep.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_osdep.h 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,116 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++
++/* glue for the OS-dependent part of e1000
++ * includes register access macros
++ */
++
++#ifndef _E1000_OSDEP_H_
++#define _E1000_OSDEP_H_
++
++#include <linux/pci.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/if_ether.h>
++
++#include "kcompat.h"
++
++#define usec_delay(x) udelay(x)
++#ifndef msec_delay
++#define msec_delay(x) do { if(in_interrupt()) { \
++ /* Don't sleep in interrupt context! */ \
++ BUG(); \
++ } else { \
++ msleep(x); \
++ } } while (0)
++
++/* Some workarounds require millisecond delays and are run during interrupt
++ * context. Most notably, when establishing link, the phy may need tweaking
++ * but cannot process phy register reads/writes faster than millisecond
++ * intervals...and we establish link due to a "link status change" interrupt.
++ */
++#define msec_delay_irq(x) mdelay(x)
++#endif
++
++#define PCI_COMMAND_REGISTER PCI_COMMAND
++#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
++#define ETH_ADDR_LEN ETH_ALEN
++
++
++#define DEBUGOUT(S)
++#define DEBUGOUT1(S, A...)
++
++#define DEBUGFUNC(F) DEBUGOUT(F "\n")
++#define DEBUGOUT2 DEBUGOUT1
++#define DEBUGOUT3 DEBUGOUT2
++#define DEBUGOUT7 DEBUGOUT3
++
++#define E1000_WRITE_REG(a, reg, value) ( \
++ writel((value), ((a)->hw_addr + reg)))
++
++#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
++
++#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
++ writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
++
++#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
++ readl((a)->hw_addr + reg + ((offset) << 2)))
++
++#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
++#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
++
++#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
++ writew((value), ((a)->hw_addr + reg + ((offset) << 1))))
++
++#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
++ readw((a)->hw_addr + reg + ((offset) << 1)))
++
++#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
++ writeb((value), ((a)->hw_addr + reg + (offset))))
++
++#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
++ readb((a)->hw_addr + reg + (offset)))
++
++#define E1000_WRITE_REG_IO(a, reg, offset) do { \
++ outl(reg, ((a)->io_base)); \
++ outl(offset, ((a)->io_base + 4)); } while(0)
++
++#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
++
++#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
++ writel((value), ((a)->flash_address + reg)))
++
++#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
++ writew((value), ((a)->flash_address + reg)))
++
++#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
++
++#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
++
++#endif /* _E1000_OSDEP_H_ */
+diff -Nurp linux-2.6.22-0/drivers/net/e1000e/e1000_phy.c linux-2.6.22-10/drivers/net/e1000e/e1000_phy.c
+--- linux-2.6.22-0/drivers/net/e1000e/e1000_phy.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.22-10/drivers/net/e1000e/e1000_phy.c 2008-10-14 01:51:32.000000000 +0200
+@@ -0,0 +1,2489 @@
++/*******************************************************************************
++
++ Intel PRO/1000 Linux driver
++ Copyright(c) 1999 - 2008 Intel Corporation.
++
++ This program is free software; you can redistribute it and/or modify it
++ under the terms and conditions of the GNU General Public License,
++ version 2, as published by the Free Software Foundation.
++
++ This program is distributed in the hope it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ more details.
++
++ You should have received a copy of the GNU General Public License along with
++ this program; if not, write to the Free Software Foundation, Inc.,
++ 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++
++ The full GNU General Public License is included in this distribution in
++ the file called "COPYING".
++
++ Contact Information:
++ Linux NICS <linux.nics@intel.com>
++ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
++ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
++
++*******************************************************************************/
++
++#include "e1000_hw.h"
++
++static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
++/* Cable length tables */
++static const u16 e1000_m88_cable_length_table[] =
++ { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
++#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
++ (sizeof(e1000_m88_cable_length_table) / \
++ sizeof(e1000_m88_cable_length_table[0]))
++
++static const u16 e1000_igp_2_cable_length_table[] =
++ { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
++ 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
++ 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
++ 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
++ 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
++ 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
++ 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
++ 104, 109, 114, 118, 121, 124};
++#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
++ (sizeof(e1000_igp_2_cable_length_table) / \
++ sizeof(e1000_igp_2_cable_length_table[0]))
++
++/**
++ * e1000_check_reset_block_generic - Check if PHY reset is blocked
++ * @hw: pointer to the HW structure
++ *
++ * Read the PHY management control register and check whether a PHY reset
++ * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
++ * return E1000_BLK_PHY_RESET (12).
++ **/
++s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
++{
++ u32 manc;
++
++ DEBUGFUNC("e1000_check_reset_block");
++
++ manc = E1000_READ_REG(hw, E1000_MANC);
++
++ return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
++ E1000_BLK_PHY_RESET : E1000_SUCCESS;
++}
++
++/**
++ * e1000_get_phy_id - Retrieve the PHY ID and revision
++ * @hw: pointer to the HW structure
++ *
++ * Reads the PHY registers and stores the PHY ID and possibly the PHY
++ * revision in the hardware structure.
++ **/
++s32 e1000_get_phy_id(struct e1000_hw *hw)
++{
++ struct e1000_phy_info *phy = &hw->phy;
++ s32 ret_val = E1000_SUCCESS;
++ u16 phy_id;
++
++ DEBUGFUNC("e1000_get_phy_id");
++
++ if (!(phy->ops.read_reg))
++ goto out;
++
++ ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
++ if (ret_val)
++ goto out;
++
++ phy->id = (u32)(phy_id << 16);
++ usec_delay(20);
++ ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
++ if (ret_val)
++ goto out;
++
++ phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
++ phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_phy_reset_dsp_generic - Reset PHY DSP
++ * @hw: pointer to the HW structure
++ *
++ * Reset the digital signal processor.
++ **/
++s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_phy_reset_dsp_generic");
++
++ if (!(hw->phy.ops.write_reg))
++ goto out;
++
++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
++ if (ret_val)
++ goto out;
++
++ ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_phy_reg_mdic - Read MDI control register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to be read
++ * @data: pointer to the read data
++ *
++ * Reads the MDI control register in the PHY at offset and stores the
++ * information read to data.
++ **/
++s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
++{
++ struct e1000_phy_info *phy = &hw->phy;
++ u32 i, mdic = 0;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_read_phy_reg_mdic");
++
++ /*
++ * Set up Op-code, Phy Address, and register offset in the MDI
++ * Control register. The MAC will take care of interfacing with the
++ * PHY to retrieve the desired data.
++ */
++ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
++ (phy->addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_READ));
++
++ E1000_WRITE_REG(hw, E1000_MDIC, mdic);
++
++ /*
++ * Poll the ready bit to see if the MDI read completed
++ * Increasing the time out as testing showed failures with
++ * the lower time out
++ */
++ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
++ usec_delay(50);
++ mdic = E1000_READ_REG(hw, E1000_MDIC);
++ if (mdic & E1000_MDIC_READY)
++ break;
++ }
++ if (!(mdic & E1000_MDIC_READY)) {
++ DEBUGOUT("MDI Read did not complete\n");
++ ret_val = -E1000_ERR_PHY;
++ goto out;
++ }
++ if (mdic & E1000_MDIC_ERROR) {
++ DEBUGOUT("MDI Error\n");
++ ret_val = -E1000_ERR_PHY;
++ goto out;
++ }
++ *data = (u16) mdic;
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_write_phy_reg_mdic - Write MDI control register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to write to
++ * @data: data to write to register at offset
++ *
++ * Writes data to MDI control register in the PHY at offset.
++ **/
++s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
++{
++ struct e1000_phy_info *phy = &hw->phy;
++ u32 i, mdic = 0;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_write_phy_reg_mdic");
++
++ /*
++ * Set up Op-code, Phy Address, and register offset in the MDI
++ * Control register. The MAC will take care of interfacing with the
++ * PHY to retrieve the desired data.
++ */
++ mdic = (((u32)data) |
++ (offset << E1000_MDIC_REG_SHIFT) |
++ (phy->addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_WRITE));
++
++ E1000_WRITE_REG(hw, E1000_MDIC, mdic);
++
++ /*
++ * Poll the ready bit to see if the MDI read completed
++ * Increasing the time out as testing showed failures with
++ * the lower time out
++ */
++ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
++ usec_delay(50);
++ mdic = E1000_READ_REG(hw, E1000_MDIC);
++ if (mdic & E1000_MDIC_READY)
++ break;
++ }
++ if (!(mdic & E1000_MDIC_READY)) {
++ DEBUGOUT("MDI Write did not complete\n");
++ ret_val = -E1000_ERR_PHY;
++ goto out;
++ }
++ if (mdic & E1000_MDIC_ERROR) {
++ DEBUGOUT("MDI Error\n");
++ ret_val = -E1000_ERR_PHY;
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_phy_reg_m88 - Read m88 PHY register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to be read
++ * @data: pointer to the read data
++ *
++ * Acquires semaphore, if necessary, then reads the PHY register at offset
++ * and storing the retrieved information in data. Release any acquired
++ * semaphores before exiting.
++ **/
++s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_read_phy_reg_m88");
++
++ if (!(hw->phy.ops.acquire))
++ goto out;
++
++ ret_val = hw->phy.ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ ret_val = e1000_read_phy_reg_mdic(hw,
++ MAX_PHY_REG_ADDRESS & offset,
++ data);
++
++ hw->phy.ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_write_phy_reg_m88 - Write m88 PHY register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to write to
++ * @data: data to write at register offset
++ *
++ * Acquires semaphore, if necessary, then writes the data to PHY register
++ * at the offset. Release any acquired semaphores before exiting.
++ **/
++s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_write_phy_reg_m88");
++
++ if (!(hw->phy.ops.acquire))
++ goto out;
++
++ ret_val = hw->phy.ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ ret_val = e1000_write_phy_reg_mdic(hw,
++ MAX_PHY_REG_ADDRESS & offset,
++ data);
++
++ hw->phy.ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_phy_reg_igp - Read igp PHY register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to be read
++ * @data: pointer to the read data
++ *
++ * Acquires semaphore, if necessary, then reads the PHY register at offset
++ * and storing the retrieved information in data. Release any acquired
++ * semaphores before exiting.
++ **/
++s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_read_phy_reg_igp");
++
++ if (!(hw->phy.ops.acquire))
++ goto out;
++
++ ret_val = hw->phy.ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ if (offset > MAX_PHY_MULTI_PAGE_REG) {
++ ret_val = e1000_write_phy_reg_mdic(hw,
++ IGP01E1000_PHY_PAGE_SELECT,
++ (u16)offset);
++ if (ret_val) {
++ hw->phy.ops.release(hw);
++ goto out;
++ }
++ }
++
++ ret_val = e1000_read_phy_reg_mdic(hw,
++ MAX_PHY_REG_ADDRESS & offset,
++ data);
++
++ hw->phy.ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_write_phy_reg_igp - Write igp PHY register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to write to
++ * @data: data to write at register offset
++ *
++ * Acquires semaphore, if necessary, then writes the data to PHY register
++ * at the offset. Release any acquired semaphores before exiting.
++ **/
++s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
++{
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_write_phy_reg_igp");
++
++ if (!(hw->phy.ops.acquire))
++ goto out;
++
++ ret_val = hw->phy.ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ if (offset > MAX_PHY_MULTI_PAGE_REG) {
++ ret_val = e1000_write_phy_reg_mdic(hw,
++ IGP01E1000_PHY_PAGE_SELECT,
++ (u16)offset);
++ if (ret_val) {
++ hw->phy.ops.release(hw);
++ goto out;
++ }
++ }
++
++ ret_val = e1000_write_phy_reg_mdic(hw,
++ MAX_PHY_REG_ADDRESS & offset,
++ data);
++
++ hw->phy.ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_read_kmrn_reg_generic - Read kumeran register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to be read
++ * @data: pointer to the read data
++ *
++ * Acquires semaphore, if necessary. Then reads the PHY register at offset
++ * using the kumeran interface. The information retrieved is stored in data.
++ * Release any acquired semaphores before exiting.
++ **/
++s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
++{
++ u32 kmrnctrlsta;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_read_kmrn_reg_generic");
++
++ if (!(hw->phy.ops.acquire))
++ goto out;
++
++ ret_val = hw->phy.ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
++ E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
++ E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
++
++ usec_delay(2);
++
++ kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
++ *data = (u16)kmrnctrlsta;
++
++ hw->phy.ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_write_kmrn_reg_generic - Write kumeran register
++ * @hw: pointer to the HW structure
++ * @offset: register offset to write to
++ * @data: data to write at register offset
++ *
++ * Acquires semaphore, if necessary. Then write the data to PHY register
++ * at the offset using the kumeran interface. Release any acquired semaphores
++ * before exiting.
++ **/
++s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
++{
++ u32 kmrnctrlsta;
++ s32 ret_val = E1000_SUCCESS;
++
++ DEBUGFUNC("e1000_write_kmrn_reg_generic");
++
++ if (!(hw->phy.ops.acquire))
++ goto out;
++
++ ret_val = hw->phy.ops.acquire(hw);
++ if (ret_val)
++ goto out;
++
++ kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
++ E1000_KMRNCTRLSTA_OFFSET) | data;
++ E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
++
++ usec_delay(2);
++ hw->phy.ops.release(hw);
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
++ * @hw: pointer to the HW structure
++ *
++ * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
++ * and downshift values are set also.
++ **/
++s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
++{
++ struct e1000_phy_info *phy = &hw->phy;
++ s32 ret_val;
++ u16 phy_data;
++
++ DEBUGFUNC("e1000_copper_link_setup_m88");
++
++ if (phy->reset_disable) {
++ ret_val = E1000_SUCCESS;
++ goto out;
++ }
++
++ /* Enable CRS on TX. This must be set for half-duplex operation. */
++ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
++ if (ret_val)
++ goto out;
++
++ /* For newer PHYs this bit is downshift enable */
++ if (phy->type == e1000_phy_m88)
++ phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
++
++ /*
++ * Options:
++ * MDI/MDI-X = 0 (default)
++ * 0 - Auto for all speeds
++ * 1 - MDI mode
++ * 2 - MDI-X mode
++ * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
++ */
++ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
++
++ switch (phy->mdix) {
++ case 1:
++ phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
++ break;
++ case 2:
++ phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
++ break;
++ case 3:
++ phy_data |= M88E1000_PSCR_AUTO_X_1000T;
++ break;
++ case 0:
++ default:
++ phy_data |= M88E1000_PSCR_AUTO_X_MODE;
++ break;
++ }
++
++ /*
++ * Options:
++ * disable_polarity_correction = 0 (default)
++ * Automatic Correction for Reversed Cable Polarity
++ * 0 - Disabled
++ * 1 - Enabled
++ */
++ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
++ if (phy->disable_polarity_correction == 1)
++ phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
++
++ /* Enable downshift on BM (disabled by default) */
++ if (phy->type == e1000_phy_bm)
++ phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
++
++ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
++ if (ret_val)
++ goto out;
++
++ if ((phy->type == e1000_phy_m88) &&
++ (phy->revision < E1000_REVISION_4) &&
++ (phy->id != BME1000_E_PHY_ID_R2)) {
++ /*
++ * Force TX_CLK in the Extended PHY Specific Control Register
++ * to 25MHz clock.
++ */
++ ret_val = phy->ops.read_reg(hw,
++ M88E1000_EXT_PHY_SPEC_CTRL,
++ &phy_data);
++ if (ret_val)
++ goto out;
++
++ phy_data |= M88E1000_EPSCR_TX_CLK_25;
++
++ if ((phy->revision == E1000_REVISION_2) &&
++ (phy->id == M88E1111_I_PHY_ID)) {
++ /* 82573L PHY - set the downshift counter to 5x. */
++ phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
++ phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
++ } else {
++ /* Configure Master and Slave downshift values */
++ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
++ phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
++ M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
++ }
++ ret_val = phy->ops.write_reg(hw,
++ M88E1000_EXT_PHY_SPEC_CTRL,
++ phy_data);
++ if (ret_val)
++ goto out;
++ }
++
++ if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
++ /* Set PHY page 0, register 29 to 0x0003 */
++ ret_val = phy->ops.write_reg(hw, 29, 0x0003);
++ if (ret_val)
++ goto out;
++
++ /* Set PHY page 0, register 30 to 0x0000 */
++ ret_val = phy->ops.write_reg(hw, 30, 0x0000);
++ if (ret_val)
++ goto out;
++ }
++
++ /* Commit the changes. */
++ ret_val = phy->ops.commit(hw);
++ if (ret_val) {
++ DEBUGOUT("Error committing the PHY changes\n");
++ goto out;
++ }
++
++out:
++ return ret_val;
++}
++
++/**
++ * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
++ * @hw: pointer to the HW structure
++ *
++ * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
++ * igp PHY's.
++ **/
++s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
++{
++ struct e1000_phy_info *phy = &hw->phy;
++ s32 ret_val;
++ u16 data;