- for (i = 1; i < 10; i++)
- {
- switch (i)
- {
- case 1: /* Host interrupt enable */
- sscape_write(devc, i, 0xf0); /* All interrupts enabled */
- break;
-
- case 2: /* DMA A status/trigger register */
- case 3: /* DMA B status/trigger register */
- sscape_write(devc, i, 0x20); /* DMA channel disabled */
- break;
-
- case 4: /* Host interrupt config reg */
- sscape_write(devc, i, 0xf0 | (irq_bits << 2) | irq_bits);
- break;
-
- case 5: /* Don't destroy CD-ROM DMA config bits (0xc0) */
- sscape_write(devc, i, (regs[i] & 0x3f) | (sscape_read(devc, i) & 0xc0));
- break;
-
- case 6: /* CD-ROM config (WSS codec actually) */
- sscape_write(devc, i, regs[i]);
- break;
-
- case 9: /* Master control reg. Don't modify CR-ROM bits. Disable SB emul */
- sscape_write(devc, i, (sscape_read(devc, i) & 0xf0) | 0x08);
- break;
-
- default:
- sscape_write(devc, i, regs[i]);
- }
- }
+ /* Host interrupt enable */
+ sscape_write(devc, 1, 0xf0); /* All interrupts enabled */
+ /* DMA A status/trigger register */
+ sscape_write(devc, 2, 0x20); /* DMA channel disabled */
+ /* DMA B status/trigger register */
+ sscape_write(devc, 3, 0x20); /* DMA channel disabled */
+ /* Host interrupt config reg */
+ sscape_write(devc, 4, 0xf0 | (irq_bits << 2) | irq_bits);
+ /* Don't destroy CD-ROM DMA config bits (0xc0) */
+ sscape_write(devc, 5, (regs[5] & 0x3f) | (sscape_read(devc, 5) & 0xc0));
+ /* CD-ROM config (WSS codec actually) */
+ sscape_write(devc, 6, regs[6]);
+ sscape_write(devc, 7, regs[7]);
+ sscape_write(devc, 8, regs[8]);
+ /* Master control reg. Don't modify CR-ROM bits. Disable SB emul */
+ sscape_write(devc, 9, (sscape_read(devc, 9) & 0xf0) | 0x08);