vserver 1.9.3

[linux-2.6.git] / Documentation / cachetlb.txt

diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt
index 094631f..9e2f988 100644 (file)
--- a/Documentation/cachetlb.txt
+++ b/Documentation/cachetlb.txt
@@ -132,6 +132,17 @@ changes occur:
        translations for software managed TLB configurations.
        The sparc64 port currently does this.
 
+7) void tlb_migrate_finish(struct mm_struct *mm)
+
+       This interface is called at the end of an explicit
+       process migration. This interface provides a hook
+       to allow a platform to update TLB or context-specific
+       information for the address space.
+
+       The ia64 sn2 platform is one example of a platform
+       that uses this interface.
+
+
 Next, we have the cache flushing interfaces.  In general, when Linux
 is changing an existing virtual-->physical mapping to a new value,
 the sequence will be in one of the following forms:
@@ -322,10 +333,10 @@ maps this page at its virtual address.
        about doing this.
 
        The idea is, first at flush_dcache_page() time, if
-       page->mapping->i_mmap{,_shared} are empty lists, just mark the
-       architecture private page flag bit.  Later, in
-       update_mmu_cache(), a check is made of this flag bit, and if
-       set the flush is done and the flag bit is cleared.
+       page->mapping->i_mmap is an empty tree and ->i_mmap_nonlinear
+       an empty list, just mark the architecture private page flag bit.
+       Later, in update_mmu_cache(), a check is made of this flag bit,
+       and if set the flush is done and the flag bit is cleared.
 
        IMPORTANT NOTE: It is often important, if you defer the flush,
                        that the actual flush occurs on the same CPU
@@ -343,10 +354,6 @@ maps this page at its virtual address.
        of arbitrary user pages (f.e. for ptrace()) it will use
        these two routines.
 
-       The page has been kmap()'d, and flush_cache_page() has
-       just been called for the user mapping of this page (if
-       necessary).
-
        Any necessary cache flushing or other coherency operations
        that need to occur should happen here.  If the processor's
        instruction cache does not snoop cpu stores, it is very