#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
+#include <linux/bitops.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/dma.h>
#include <asm/irq.h>
-#include <asm/bitops.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
/* dp264 boards handle at max four CPUs */
static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
-spinlock_t dp264_irq_lock = SPIN_LOCK_UNLOCKED;
+DEFINE_SPINLOCK(dp264_irq_lock);
static void
tsunami_update_irq_hw(unsigned long mask)
dim1 = &cchip->dim1.csr;
dim2 = &cchip->dim2.csr;
dim3 = &cchip->dim3.csr;
- if (cpu_possible(0)) dim0 = &dummy;
- if (cpu_possible(1)) dim1 = &dummy;
- if (cpu_possible(2)) dim2 = &dummy;
- if (cpu_possible(3)) dim3 = &dummy;
+ if (!cpu_possible(0)) dim0 = &dummy;
+ if (!cpu_possible(1)) dim1 = &dummy;
+ if (!cpu_possible(2)) dim2 = &dummy;
+ if (!cpu_possible(3)) dim3 = &dummy;
*dim0 = mask0;
*dim1 = mask1;
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,