#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
+#include <linux/bitops.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/dma.h>
#include <asm/irq.h>
-#include <asm/bitops.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
/* dp264 boards handle at max four CPUs */
static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
-spinlock_t dp264_irq_lock = SPIN_LOCK_UNLOCKED;
+DEFINE_SPINLOCK(dp264_irq_lock);
static void
tsunami_update_irq_hw(unsigned long mask)
register int bcpu = boot_cpuid;
#ifdef CONFIG_SMP
- register unsigned long cpm = cpu_present_mask;
volatile unsigned long *dim0, *dim1, *dim2, *dim3;
unsigned long mask0, mask1, mask2, mask3, dummy;
dim1 = &cchip->dim1.csr;
dim2 = &cchip->dim2.csr;
dim3 = &cchip->dim3.csr;
- if ((cpm & 1) == 0) dim0 = &dummy;
- if ((cpm & 2) == 0) dim1 = &dummy;
- if ((cpm & 4) == 0) dim2 = &dummy;
- if ((cpm & 8) == 0) dim3 = &dummy;
+ if (!cpu_possible(0)) dim0 = &dummy;
+ if (!cpu_possible(1)) dim1 = &dummy;
+ if (!cpu_possible(2)) dim2 = &dummy;
+ if (!cpu_possible(3)) dim3 = &dummy;
*dim0 = mask0;
*dim1 = mask1;
}
static void
-cpu_set_irq_affinity(unsigned int irq, unsigned long affinity)
+cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
{
int cpu;
for (cpu = 0; cpu < 4; cpu++) {
unsigned long aff = cpu_irq_affinity[cpu];
- if (affinity & (1UL << cpu))
+ if (cpu_isset(cpu, affinity))
aff |= 1UL << irq;
else
aff &= ~(1UL << irq);
}
static void
-dp264_set_affinity(unsigned int irq, unsigned long affinity)
+dp264_set_affinity(unsigned int irq, cpumask_t affinity)
{
spin_lock(&dp264_irq_lock);
cpu_set_irq_affinity(irq, affinity);
}
static void
-clipper_set_affinity(unsigned int irq, unsigned long affinity)
+clipper_set_affinity(unsigned int irq, cpumask_t affinity)
{
spin_lock(&dp264_irq_lock);
cpu_set_irq_affinity(irq - 16, affinity);
* 10 64 bit PCI option slot 3 (not bus 0)
*/
+static int __init
+isa_irq_fixup(struct pci_dev *dev, int irq)
+{
+ u8 irq8;
+
+ if (irq > 0)
+ return irq;
+
+ /* This interrupt is routed via ISA bridge, so we'll
+ just have to trust whatever value the console might
+ have assigned. */
+ pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
+
+ return irq8 & 0xf;
+}
+
static int __init
dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
{ 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
};
const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
-
struct pci_controller *hose = dev->sysdata;
int irq = COMMON_TABLE_LOOKUP;
- if (irq > 0) {
+ if (irq > 0)
irq += 16 * hose->index;
- } else {
- /* ??? The Contaq IDE controller on the ISA bridge uses
- "legacy" interrupts 14 and 15. I don't know if anything
- can wind up at the same slot+pin on hose1, so we'll
- just have to trust whatever value the console might
- have assigned. */
-
- u8 irq8;
- pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
- irq = irq8;
- }
- return irq;
+ return isa_irq_fixup(dev, irq);
}
static int __init
{ 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
};
const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
- return COMMON_TABLE_LOOKUP;
+
+ return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
}
static u8 __init
{ 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
};
const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
- return COMMON_TABLE_LOOKUP;
+
+ return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
}
static int __init
{ -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
};
const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
-
struct pci_controller *hose = dev->sysdata;
int irq = COMMON_TABLE_LOOKUP;
if (irq > 0)
irq += 16 * hose->index;
- return irq;
+ return isa_irq_fixup(dev, irq);
}
static void __init
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TSUNAMI_IO,
- DO_TSUNAMI_BUS,
.machine_check = tsunami_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,