* Please select one of the following when turning on debugging.
*/
#ifdef DEBUG
-#if defined(CONFIG_DEBUG_DC21285_PORT)
- .macro loadsp, rb
- mov \rb, #0x42000000
- .endm
- .macro writeb, rb
- str \rb, [r3, #0x160]
- .endm
-#elif defined(CONFIG_DEBUG_ICEDCC)
- .macro loadsp, rb
- .endm
- .macro writeb, rb
- mcr p14, 0, \rb, c0, c1, 0
- .endm
-#elif defined(CONFIG_FOOTBRIDGE)
- .macro loadsp, rb
- mov \rb, #0x7c000000
- .endm
- .macro writeb, rb
- strb \rb, [r3, #0x3f8]
- .endm
-#elif defined(CONFIG_ARCH_RPC)
- .macro loadsp, rb
- mov \rb, #0x03000000
- orr \rb, \rb, #0x00010000
- .endm
- .macro writeb, rb
- strb \rb, [r3, #0x3f8 << 2]
- .endm
-#elif defined(CONFIG_ARCH_INTEGRATOR)
+
+#if defined(CONFIG_DEBUG_ICEDCC)
.macro loadsp, rb
- mov \rb, #0x16000000
- .endm
- .macro writeb, rb
- strb \rb, [r3, #0]
.endm
-#elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
- .macro loadsp, rb
- mov \rb, #0x40000000
- orr \rb, \rb, #0x00100000
+ .macro writeb, ch, rb
+ mcr p14, 0, \ch, c0, c1, 0
.endm
- .macro writeb, rb
- strb \rb, [r3, #0]
+#else
+
+#include <asm/arch/debug-macro.S>
+
+ .macro writeb, ch, rb
+ senduart \ch, \rb
.endm
-#elif defined(CONFIG_ARCH_SA1100)
+
+#if defined(CONFIG_ARCH_SA1100)
.macro loadsp, rb
mov \rb, #0x80000000 @ physical base address
-# if defined(CONFIG_DEBUG_LL_SER3)
+#ifdef CONFIG_DEBUG_LL_SER3
add \rb, \rb, #0x00050000 @ Ser3
-# else
+#else
add \rb, \rb, #0x00010000 @ Ser1
-# endif
- .endm
- .macro writeb, rb
- str \rb, [r3, #0x14] @ UTDR
+#endif
.endm
-#elif defined(CONFIG_ARCH_IXP4XX)
- .macro loadsp, rb
- mov \rb, #0xc8000000
+#elif defined(CONFIG_ARCH_IOP331)
+ .macro loadsp, rb
+ mov \rb, #0xff000000
+ orr \rb, \rb, #0x00ff0000
+ orr \rb, \rb, #0x0000f700 @ location of the UART
.endm
- .macro writeb, rb
- str \rb, [r3, #0]
-#elif defined(CONFIG_ARCH_LH7A40X)
- .macro loadsp, rb
- ldr \rb, =0x80000700 @ UART2 UARTBASE
+#elif defined(CONFIG_ARCH_S3C2410)
+ .macro loadsp, rb
+ mov \rb, #0x50000000
+ add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
.endm
- .macro writeb, rb
- strb \rb, [r3, #0]
+#else
+ .macro loadsp, rb
+ addruart \rb
.endm
-#elif defined(CONFIG_ARCH_OMAP)
- .macro loadsp, rb
- mov \rb, #0xff000000 @ physical base address
- add \rb, \rb, #0x00fb0000
-#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
- add \rb, \rb, #0x00000800
#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
- add \rb, \rb, #0x00009000
-#endif
- .endm
- .macro writeb, rb
- strb \rb, [r3]
- .endm
-#else
-#error no serial architecture defined
#endif
#endif
kputc #'\n'
kphex r5, 8 /* decompressed kernel start */
kputc #'-'
- kphex r8, 8 /* decompressed kernel end */
+ kphex r9, 8 /* decompressed kernel end */
kputc #'>'
kphex r4, 8 /* kernel execution address */
kputc #'\n'
.word start @ absolute load/run zImage address
.word _edata @ zImage end address
1: mov r7, r1 @ save architecture ID
- mov r8, #0 @ save r0
+ mov r8, r2 @ save atags pointer
#ifndef __ARM_ARCH_2__
/*
/*
* some architecture specific code can be inserted
- * by the linker here, but it should preserve r7 and r8.
+ * by the linker here, but it should preserve r7, r8, and r9.
*/
.text
* r5 = decompressed kernel start
* r6 = processor ID
* r7 = architecture ID
- * r8-r14 = unused
+ * r8 = atags pointer
+ * r9-r14 = corrupted
*/
add r1, r5, r0 @ end of decompressed kernel
adr r2, reloc_start
ldr r3, LC1
add r3, r2, r3
-1: ldmia r2!, {r8 - r13} @ copy relocation code
- stmia r1!, {r8 - r13}
- ldmia r2!, {r8 - r13}
- stmia r1!, {r8 - r13}
+1: ldmia r2!, {r9 - r14} @ copy relocation code
+ stmia r1!, {r9 - r14}
+ ldmia r2!, {r9 - r14}
+ stmia r1!, {r9 - r14}
cmp r2, r3
blo 1b
LC1: .word reloc_end - reloc_start
.size LC0, . - LC0
+#ifdef CONFIG_ARCH_RPC
+ .globl params
+params: ldr r0, =params_phys
+ mov pc, lr
+ .ltorg
+ .align
+#endif
+
/*
* Turn on the cache. We need to setup some page tables so that we
* can have both the I and D caches on.
* r4 = kernel execution address
* r6 = processor ID
* r7 = architecture number
- * r8 = run-time address of "start"
+ * r8 = atags pointer
+ * r9 = run-time address of "start" (???)
* On exit,
- * r1, r2, r3, r8, r9, r12 corrupted
+ * r1, r2, r3, r9, r10, r12 corrupted
* This routine must preserve:
- * r4, r5, r6, r7
+ * r4, r5, r6, r7, r8
*/
.align 5
cache_on: mov r3, #8 @ cache_on function
* bits for the RAM area only.
*/
mov r0, r3
- mov r8, r0, lsr #18
- mov r8, r8, lsl #18 @ start of RAM
- add r9, r8, #0x10000000 @ a reasonable RAM size
+ mov r9, r0, lsr #18
+ mov r9, r9, lsl #18 @ start of RAM
+ add r10, r9, #0x10000000 @ a reasonable RAM size
mov r1, #0x12
orr r1, r1, #3 << 10
add r2, r3, #16384
-1: cmp r1, r8 @ if virt > start of RAM
+1: cmp r1, r9 @ if virt > start of RAM
orrhs r1, r1, #0x0c @ set cacheable, bufferable
- cmp r1, r9 @ if virt > end of RAM
+ cmp r1, r10 @ if virt > end of RAM
bichs r1, r1, #0x0c @ clear cacheable, bufferable
str r1, [r0], #4 @ 1:1 mapping
add r1, r1, #1048576
* r5 = decompressed kernel start
* r6 = processor ID
* r7 = architecture ID
- * r8-r14 = unused
+ * r8 = atags pointer
+ * r9-r14 = corrupted
*/
.align 5
-reloc_start: add r8, r5, r0
+reloc_start: add r9, r5, r0
debug_reloc_start
mov r1, r4
1:
.rept 4
- ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
- stmia r1!, {r0, r2, r3, r9 - r13}
+ ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
+ stmia r1!, {r0, r2, r3, r10 - r14}
.endr
- cmp r5, r8
+ cmp r5, r9
blo 1b
debug_reloc_end
call_kernel: bl cache_clean_flush
bl cache_off
- mov r0, #0
+ mov r0, #0 @ must be zero
mov r1, r7 @ restore architecture number
+ mov r2, r8 @ restore atags pointer
mov pc, r4 @ call kernel
/*
b __armv4_cache_off
b __armv4_cache_flush
+ .word 0x00070000 @ ARMv6
+ .word 0x000f0000
+ b __armv4_cache_on
+ b __armv4_cache_off
+ b __armv6_cache_flush
+
.word 0 @ unrecognised type
.word 0
mov pc, lr
mov r3, #16
b call_cache_fn
+__armv6_cache_flush:
+ mov r1, #0
+ mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
+ mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
+ mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
+ mcr p15, 0, r1, c7, c10, 4 @ drain WB
+ mov pc, lr
+
__armv4_cache_flush:
mov r2, #64*1024 @ default: 32K dcache size (*2)
mov r11, #32 @ default: 32 byte line size
1: ldrb r2, [r0], #1
teq r2, #0
moveq pc, lr
-2: writeb r2
+2: writeb r2, r3
mov r1, #0x00020000
3: subs r1, r1, #1
bne 3b