#include <asm/io.h>
#include <asm/page.h>
-static u32 __isamem_convert_addr(void *addr)
+static void __iomem *__isamem_convert_addr(void __iomem *addr)
{
- u32 ret, a = (u32) addr;
+ u32 ret, a = (u32 __force) addr;
/*
* The PCMCIA controller is wired up as follows:
ret += 0xe8000000;
if ((a & 0x20000) == (a & 0x40000) >> 1)
- return ret;
+ return (void __iomem *)ret;
BUG();
- return 0;
+ return NULL;
}
/*
* read[bwl] and write[bwl]
*/
-u8 __readb(void *addr)
+u8 __readb(void __iomem *addr)
{
- u32 ret, a = __isamem_convert_addr(addr);
+ void __iomem *a = __isamem_convert_addr(addr);
+ u32 ret;
- if ((int)addr & 1)
- ret = __raw_getl(a);
+ if ((unsigned long)addr & 1)
+ ret = __raw_readl(a);
else
- ret = __raw_getb(a);
+ ret = __raw_readb(a);
return ret;
}
-u16 __readw(void *addr)
+u16 __readw(void __iomem *addr)
{
- u32 a = __isamem_convert_addr(addr);
+ void __iomem *a = __isamem_convert_addr(addr);
- if ((int)addr & 1)
+ if ((unsigned long)addr & 1)
BUG();
- return __raw_getw(a);
+ return __raw_readw(a);
}
-u32 __readl(void *addr)
+u32 __readl(void __iomem *addr)
{
- u32 ret, a = __isamem_convert_addr(addr);
+ void __iomem *a = __isamem_convert_addr(addr);
+ u32 ret;
- if ((int)addr & 3)
+ if ((unsigned long)addr & 3)
BUG();
- ret = __raw_getw(a);
- ret |= __raw_getw(a + 4) << 16;
+ ret = __raw_readw(a);
+ ret |= __raw_readw(a + 4) << 16;
return ret;
}
EXPORT_SYMBOL(__readw);
EXPORT_SYMBOL(__readl);
-void __writeb(u8 val, void *addr)
+void __writeb(u8 val, void __iomem *addr)
{
- u32 a = __isamem_convert_addr(addr);
+ void __iomem *a = __isamem_convert_addr(addr);
- if ((int)addr & 1)
- __raw_putl(val, a);
+ if ((unsigned long)addr & 1)
+ __raw_writel(val, a);
else
- __raw_putb(val, a);
+ __raw_writeb(val, a);
}
-void __writew(u16 val, void *addr)
+void __writew(u16 val, void __iomem *addr)
{
- u32 a = __isamem_convert_addr(addr);
+ void __iomem *a = __isamem_convert_addr(addr);
- if ((int)addr & 1)
+ if ((unsigned long)addr & 1)
BUG();
- __raw_putw(val, a);
+ __raw_writew(val, a);
}
-void __writel(u32 val, void *addr)
+void __writel(u32 val, void __iomem *addr)
{
- u32 a = __isamem_convert_addr(addr);
+ void __iomem *a = __isamem_convert_addr(addr);
- if ((int)addr & 3)
+ if ((unsigned long)addr & 3)
BUG();
- __raw_putw(val, a);
- __raw_putw(val >> 16, a + 4);
+ __raw_writew(val, a);
+ __raw_writew(val >> 16, a + 4);
}
EXPORT_SYMBOL(__writeb);
((p) >> 3) == (0x2f8 >> 3) || \
((p) >> 3) == (0x378 >> 3))
-u8 __inb(int port)
+/*
+ * We're addressing an 8 or 16-bit peripheral which tranfers
+ * odd addresses on the low ISA byte lane.
+ */
+u8 __inb8(unsigned int port)
{
u32 ret;
* The SuperIO registers use sane addressing techniques...
*/
if (SUPERIO_PORT(port))
- ret = __raw_getb(ISAIO_BASE + (port << 2));
+ ret = __raw_readb(ISAIO_BASE + (port << 2));
else {
- u32 a = ISAIO_BASE + ((port & ~1) << 1);
+ void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
*/
if (port & 1)
- ret = __raw_getl(a);
+ ret = __raw_readl(a);
else
- ret = __raw_getb(a);
+ ret = __raw_readb(a);
+ }
+ return ret;
+}
+
+/*
+ * We're addressing a 16-bit peripheral which transfers odd
+ * addresses on the high ISA byte lane.
+ */
+u8 __inb16(unsigned int port)
+{
+ u32 ret;
+
+ /*
+ * The SuperIO registers use sane addressing techniques...
+ */
+ if (SUPERIO_PORT(port))
+ ret = __raw_readb(ISAIO_BASE + (port << 2));
+ else {
+ void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
+
+ /*
+ * Shame nothing else does
+ */
+ ret = __raw_readb(a + (port & 1));
}
return ret;
}
-u16 __inw(int port)
+u16 __inw(unsigned int port)
{
u32 ret;
* The SuperIO registers use sane addressing techniques...
*/
if (SUPERIO_PORT(port))
- ret = __raw_getw(ISAIO_BASE + (port << 2));
+ ret = __raw_readw(ISAIO_BASE + (port << 2));
else {
- u32 a = ISAIO_BASE + ((port & ~1) << 1);
+ void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
if (port & 1)
BUG();
- ret = __raw_getw(a);
+ ret = __raw_readw(a);
}
return ret;
}
-u32 __inl(int port)
+/*
+ * Fake a 32-bit read with two 16-bit reads. Needed for 3c589.
+ */
+u32 __inl(unsigned int port)
{
- BUG();
- return 0;
+ void __iomem *a;
+
+ if (SUPERIO_PORT(port) || port & 3)
+ BUG();
+
+ a = ISAIO_BASE + (port << 1);
+
+ return __raw_readw(a) | __raw_readw(a + 4) << 16;
}
-EXPORT_SYMBOL(__inb);
+EXPORT_SYMBOL(__inb8);
+EXPORT_SYMBOL(__inb16);
EXPORT_SYMBOL(__inw);
EXPORT_SYMBOL(__inl);
-void __outb(u8 val, int port)
+void __outb8(u8 val, unsigned int port)
{
/*
* The SuperIO registers use sane addressing techniques...
*/
if (SUPERIO_PORT(port))
- __raw_putb(val, ISAIO_BASE + (port << 2));
+ __raw_writeb(val, ISAIO_BASE + (port << 2));
else {
- u32 a = ISAIO_BASE + ((port & ~1) << 1);
+ void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
/*
* Shame nothing else does
*/
if (port & 1)
- __raw_putl(val, a);
+ __raw_writel(val, a);
else
- __raw_putb(val, a);
+ __raw_writeb(val, a);
+ }
+}
+
+void __outb16(u8 val, unsigned int port)
+{
+ /*
+ * The SuperIO registers use sane addressing techniques...
+ */
+ if (SUPERIO_PORT(port))
+ __raw_writeb(val, ISAIO_BASE + (port << 2));
+ else {
+ void __iomem *a = ISAIO_BASE + ((port & ~1) << 1);
+
+ /*
+ * Shame nothing else does
+ */
+ __raw_writeb(val, a + (port & 1));
}
}
-void __outw(u16 val, int port)
+void __outw(u16 val, unsigned int port)
{
u32 off;
if (SUPERIO_PORT(port))
off = port << 2;
else {
- off = (port & ~1) << 1;
+ off = port << 1;
if (port & 1)
BUG();
}
- __raw_putw(val, ISAIO_BASE + off);
+ __raw_writew(val, ISAIO_BASE + off);
}
-void __outl(u32 val, int port)
+void __outl(u32 val, unsigned int port)
{
BUG();
}
-EXPORT_SYMBOL(__outb);
+EXPORT_SYMBOL(__outb8);
+EXPORT_SYMBOL(__outb16);
EXPORT_SYMBOL(__outw);
EXPORT_SYMBOL(__outl);
EXPORT_SYMBOL(outsw);
EXPORT_SYMBOL(insw);
+/*
+ * We implement these as 16-bit insw/outsw, mainly for
+ * 3c589 cards.
+ */
void outsl(unsigned int port, const void *from, int len)
{
- panic("outsl not supported on this architecture");
+ u32 off = port << 1;
+
+ if (SUPERIO_PORT(port) || port & 3)
+ BUG();
+
+ __raw_writesw(ISAIO_BASE + off, from, len << 1);
}
void insl(unsigned int port, void *from, int len)
{
- panic("insl not supported on this architecture");
+ u32 off = port << 1;
+
+ if (SUPERIO_PORT(port) || port & 3)
+ BUG();
+
+ __raw_readsw(ISAIO_BASE + off, from, len << 1);
}
+
+EXPORT_SYMBOL(outsl);
+EXPORT_SYMBOL(insl);
git://git.onelab.eu / linux-2.6.git / blobdiff