#define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
-static int ep93xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static int ep93xx_timer_interrupt(int irq, void *dev_id)
{
write_seqlock(&xtime_lock);
(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
>= TIMER4_TICKS_PER_JIFFY) {
last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
- timer_tick(regs);
+ timer_tick();
}
write_sequnlock(&xtime_lock);
* EP93xx IRQ handling
*************************************************************************/
static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
- struct irqdesc *desc, struct pt_regs *regs)
+ struct irq_desc *desc)
{
unsigned char status;
int i;
for (i = 0; i < 8; i++) {
if (status & (1 << i)) {
desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
- desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc, regs);
+ desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc);
}
}
for (i = 0; i < 8; i++) {
if (status & (1 << i)) {
desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
- desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc, regs);
+ desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc);
}
}
}
return 0;
}
-static struct irqchip ep93xx_gpio_ab_irq_chip = {
+static struct irq_chip ep93xx_gpio_ab_irq_chip = {
.ack = ep93xx_gpio_ab_irq_mask_ack,
.mask = ep93xx_gpio_ab_irq_mask,
.unmask = ep93xx_gpio_ab_irq_unmask,
for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
- set_irq_handler(irq, do_level_IRQ);
+ set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
platform_device_register(&ep93xx_rtc_device);
platform_device_register(&ep93xx_ohci_device);
+
+#ifdef CONFIG_CRUNCH
+ elf_hwcap |= HWCAP_CRUNCH;
+#endif
}