#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
-#include <linux/device.h>
+#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <linux/pm.h>
+#include <linux/string.h>
+
+#include <linux/sched.h>
+#include <asm/cnt32_to_63.h>
+#include <asm/div64.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
+#include <asm/arch/pxa-regs.h>
#include <asm/arch/udc.h>
+#include <asm/arch/pxafb.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/irda.h>
+#include <asm/arch/i2c.h>
#include "generic.h"
/*
- * Various clock factors driven by the CCCR register.
- */
-
-/* Crystal Frequency to Memory Frequency Multiplier (L) */
-static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
-
-/* Memory Frequency to Run Mode Frequency Multiplier (M) */
-static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
-
-/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
-/* Note: we store the value N * 2 here. */
-static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
-
-/* Crystal clock */
-#define BASE_CLK 3686400
-
-/*
- * Get the clock frequency as reflected by CCCR and the turbo flag.
- * We assume these values have been applied via a fcs.
- * If info is not 0 we also display the current settings.
+ * This is the PXA2xx sched_clock implementation. This has a resolution
+ * of at least 308ns and a maximum value that depends on the value of
+ * CLOCK_TICK_RATE.
+ *
+ * The return value is guaranteed to be monotonic in that range as
+ * long as there is always less than 582 seconds between successive
+ * calls to this function.
*/
-unsigned int get_clk_frequency_khz(int info)
+unsigned long long sched_clock(void)
{
- unsigned long cccr, turbo;
- unsigned int l, L, m, M, n2, N;
-
- cccr = CCCR;
- asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
-
- l = L_clk_mult[(cccr >> 0) & 0x1f];
- m = M_clk_mult[(cccr >> 5) & 0x03];
- n2 = N2_clk_mult[(cccr >> 7) & 0x07];
-
- L = l * BASE_CLK;
- M = m * L;
- N = n2 * M / 2;
-
- if(info)
+ unsigned long long v = cnt32_to_63(OSCR);
+ /* Note: top bit ov v needs cleared unless multiplier is even. */
+
+#if CLOCK_TICK_RATE == 3686400
+ /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
+ /* The <<1 is used to get rid of tick.hi top bit */
+ v *= 78125<<1;
+ do_div(v, 288<<1);
+#elif CLOCK_TICK_RATE == 3250000
+ /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
+ v *= 4000;
+ do_div(v, 13);
+#elif CLOCK_TICK_RATE == 3249600
+ /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
+ v *= 625000;
+ do_div(v, 2031);
+#else
+#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
+ /*
+ * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
+ * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
+ * years range and truncation to unsigned long long limits it to
+ * sched_clock's max range of ~584 years. This is nice but with
+ * higher computation cost.
+ */
{
- L += 5000;
- printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
- L / 1000000, (L % 1000000) / 10000, l );
- M += 5000;
- printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
- M / 1000000, (M % 1000000) / 10000, m );
- N += 5000;
- printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
- N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
- (turbo & 1) ? "" : "in" );
+ union {
+ unsigned long long val;
+ struct { unsigned long lo, hi; };
+ } x;
+ unsigned long long y;
+
+ x.val = v;
+ x.hi &= 0x7fffffff;
+ y = (unsigned long long)x.lo * NSEC_PER_SEC;
+ x.lo = y;
+ y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
+ x.hi = do_div(y, CLOCK_TICK_RATE);
+ do_div(x.val, CLOCK_TICK_RATE);
+ x.hi += y;
+ v = x.val;
}
+#endif
- return (turbo & 1) ? (N/1000) : (M/1000);
+ return v;
}
-EXPORT_SYMBOL(get_clk_frequency_khz);
-
-/*
- * Return the current lclk requency in units of 10kHz
- */
-unsigned int get_lclk_frequency_10khz(void)
-{
- return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
-}
-
-EXPORT_SYMBOL(get_lclk_frequency_10khz);
-
/*
* Handy function to set GPIO alternate functions
*/
int gafr;
local_irq_save(flags);
+ if (gpio_mode & GPIO_DFLT_LOW)
+ GPCR(gpio) = GPIO_bit(gpio);
+ else if (gpio_mode & GPIO_DFLT_HIGH)
+ GPSR(gpio) = GPIO_bit(gpio);
if (gpio_mode & GPIO_MD_MASK_DIR)
GPDR(gpio) |= GPIO_bit(gpio);
else
EXPORT_SYMBOL(pxa_gpio_mode);
/*
- * Note that 0xfffe0000-0xffffffff is reserved for the vector table and
- * cache flush area.
+ * Routine to safely enable or disable a clock in the CKEN
+ */
+void pxa_set_cken(int clock, int enable)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+
+ if (enable)
+ CKEN |= clock;
+ else
+ CKEN &= ~clock;
+
+ local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(pxa_set_cken);
+
+/*
+ * Intel PXA2xx internal register mapping.
+ *
+ * Note 1: not all PXA2xx variants implement all those addresses.
+ *
+ * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
+ * and cache flush area.
*/
static struct map_desc standard_io_desc[] __initdata = {
- /* virtual physical length type */
- { 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */
- { 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */
- { 0xf8000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */
- { 0xfa000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
- { 0xfc000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
- { 0xff000000, 0x00000000, 0x00100000, MT_DEVICE } /* UNCACHED_PHYS_0 */
+ { /* Devs */
+ .virtual = 0xf2000000,
+ .pfn = __phys_to_pfn(0x40000000),
+ .length = 0x02000000,
+ .type = MT_DEVICE
+ }, { /* LCD */
+ .virtual = 0xf4000000,
+ .pfn = __phys_to_pfn(0x44000000),
+ .length = 0x00100000,
+ .type = MT_DEVICE
+ }, { /* Mem Ctl */
+ .virtual = 0xf6000000,
+ .pfn = __phys_to_pfn(0x48000000),
+ .length = 0x00100000,
+ .type = MT_DEVICE
+ }, { /* USB host */
+ .virtual = 0xf8000000,
+ .pfn = __phys_to_pfn(0x4c000000),
+ .length = 0x00100000,
+ .type = MT_DEVICE
+ }, { /* Camera */
+ .virtual = 0xfa000000,
+ .pfn = __phys_to_pfn(0x50000000),
+ .length = 0x00100000,
+ .type = MT_DEVICE
+ }, { /* IMem ctl */
+ .virtual = 0xfe000000,
+ .pfn = __phys_to_pfn(0x58000000),
+ .length = 0x00100000,
+ .type = MT_DEVICE
+ }, { /* UNCACHED_PHYS_0 */
+ .virtual = 0xff000000,
+ .pfn = __phys_to_pfn(0x00000000),
+ .length = 0x00100000,
+ .type = MT_DEVICE
+ }
};
void __init pxa_map_io(void)
static u64 pxamci_dmamask = 0xffffffffUL;
static struct platform_device pxamci_device = {
- .name = "pxamci",
- .id = 0,
+ .name = "pxa2xx-mci",
+ .id = -1,
.dev = {
.dma_mask = &pxamci_dmamask,
+ .coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxamci_resources),
.resource = pxamci_resources,
};
+void __init pxa_set_mci_info(struct pxamci_platform_data *info)
+{
+ pxamci_device.dev.platform_data = info;
+}
+
static struct pxa2xx_udc_mach_info pxa_udc_info;
{
memcpy(&pxa_udc_info, info, sizeof *info);
}
-EXPORT_SYMBOL(pxa_set_udc_info);
static struct resource pxa2xx_udc_resources[] = {
[0] = {
static u64 udc_dma_mask = ~(u32)0;
static struct platform_device udc_device = {
- .name = "pxa2xx_udc",
- .id = 0,
+ .name = "pxa2xx-udc",
+ .id = -1,
.resource = pxa2xx_udc_resources,
.num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
.dev = {
}
};
+static struct resource pxafb_resources[] = {
+ [0] = {
+ .start = 0x44000000,
+ .end = 0x4400ffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_LCD,
+ .end = IRQ_LCD,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 fb_dma_mask = ~(u64)0;
+
+static struct platform_device pxafb_device = {
+ .name = "pxa2xx-fb",
+ .id = -1,
+ .dev = {
+ .dma_mask = &fb_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxafb_resources),
+ .resource = pxafb_resources,
+};
+
+void __init set_pxa_fb_info(struct pxafb_mach_info *info)
+{
+ pxafb_device.dev.platform_data = info;
+}
+
+void __init set_pxa_fb_parent(struct device *parent_dev)
+{
+ pxafb_device.dev.parent = parent_dev;
+}
+
+static struct platform_device ffuart_device = {
+ .name = "pxa2xx-uart",
+ .id = 0,
+};
+static struct platform_device btuart_device = {
+ .name = "pxa2xx-uart",
+ .id = 1,
+};
+static struct platform_device stuart_device = {
+ .name = "pxa2xx-uart",
+ .id = 2,
+};
+static struct platform_device hwuart_device = {
+ .name = "pxa2xx-uart",
+ .id = 3,
+};
+
+static struct resource i2c_resources[] = {
+ {
+ .start = 0x40301680,
+ .end = 0x403016a3,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2C,
+ .end = IRQ_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device i2c_device = {
+ .name = "pxa2xx-i2c",
+ .id = 0,
+ .resource = i2c_resources,
+ .num_resources = ARRAY_SIZE(i2c_resources),
+};
+
+void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
+{
+ i2c_device.dev.platform_data = info;
+}
+
+static struct resource i2s_resources[] = {
+ {
+ .start = 0x40400000,
+ .end = 0x40400083,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2S,
+ .end = IRQ_I2S,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device i2s_device = {
+ .name = "pxa2xx-i2s",
+ .id = -1,
+ .resource = i2s_resources,
+ .num_resources = ARRAY_SIZE(i2s_resources),
+};
+
+static u64 pxaficp_dmamask = ~(u32)0;
+
+static struct platform_device pxaficp_device = {
+ .name = "pxa2xx-ir",
+ .id = -1,
+ .dev = {
+ .dma_mask = &pxaficp_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
+{
+ pxaficp_device.dev.platform_data = info;
+}
+
+static struct platform_device pxartc_device = {
+ .name = "sa1100-rtc",
+ .id = -1,
+};
+
static struct platform_device *devices[] __initdata = {
&pxamci_device,
&udc_device,
+ &pxafb_device,
+ &ffuart_device,
+ &btuart_device,
+ &stuart_device,
+ &pxaficp_device,
+ &i2c_device,
+ &i2s_device,
+ &pxartc_device,
};
static int __init pxa_init(void)
{
- return platform_add_devices(devices, ARRAY_SIZE(devices));
+ int cpuid, ret;
+
+ ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+ if (ret)
+ return ret;
+
+ /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
+ cpuid = read_cpuid(CPUID_ID);
+ if (((cpuid >> 4) & 0xfff) == 0x2d0 ||
+ ((cpuid >> 4) & 0xfff) == 0x290)
+ ret = platform_device_register(&hwuart_device);
+
+ return ret;
}
subsys_initcall(pxa_init);