Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff

[linux-2.6.git] / arch / arm / mach-s3c2410 / gpio.c

diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 8996725..cd39e86 100644 (file)
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-s3c2410/gpio.c
  *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
+ * Copyright (c) 2004-2005 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
  *
  * S3C2410 GPIO support
  *
@@ -28,9 +28,14 @@
  *     01-Oct-2004  BJD  Fixed mask bug in pullup() call
  *     01-Oct-2004  BJD  Added getirq() to turn pin into irqno
  *     04-Oct-2004  BJD  Added irq filter controls for GPIO
+ *     05-Nov-2004  BJD  EXPORT_SYMBOL() added for all code
+ *     13-Mar-2005  BJD  Updates for __iomem
+ *     26-Oct-2005  BJD  Added generic configuration types
+ *     15-Jan-2006  LCVR Added support for the S3C2400
  */
 
 
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
@@ -44,7 +49,7 @@
 
 void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
 {
-       unsigned long base = S3C2410_GPIO_BASE(pin);
+       void __iomem *base = S3C24XX_GPIO_BASE(pin);
        unsigned long mask;
        unsigned long con;
        unsigned long flags;
@@ -55,6 +60,27 @@ void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
                mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
        }
 
+       switch (function) {
+       case S3C2410_GPIO_LEAVE:
+               mask = 0;
+               function = 0;
+               break;
+
+       case S3C2410_GPIO_INPUT:
+       case S3C2410_GPIO_OUTPUT:
+       case S3C2410_GPIO_SFN2:
+       case S3C2410_GPIO_SFN3:
+               if (pin < S3C2410_GPIO_BANKB) {
+                       function &= 1;
+                       function <<= S3C2410_GPIO_OFFSET(pin);
+               } else {
+                       function &= 3;
+                       function <<= S3C2410_GPIO_OFFSET(pin)*2;
+               }
+       }
+
+       /* modify the specified register wwith IRQs off */
+
        local_irq_save(flags);
 
        con  = __raw_readl(base + 0x00);
@@ -66,9 +92,11 @@ void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
        local_irq_restore(flags);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
+
 unsigned int s3c2410_gpio_getcfg(unsigned int pin)
 {
-       unsigned long base = S3C2410_GPIO_BASE(pin);
+       void __iomem *base = S3C24XX_GPIO_BASE(pin);
        unsigned long mask;
 
        if (pin < S3C2410_GPIO_BANKB) {
@@ -80,9 +108,11 @@ unsigned int s3c2410_gpio_getcfg(unsigned int pin)
        return __raw_readl(base) & mask;
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_getcfg);
+
 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
 {
-       unsigned long base = S3C2410_GPIO_BASE(pin);
+       void __iomem *base = S3C24XX_GPIO_BASE(pin);
        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
        unsigned long flags;
        unsigned long up;
@@ -100,9 +130,11 @@ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
        local_irq_restore(flags);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_pullup);
+
 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
 {
-       unsigned long base = S3C2410_GPIO_BASE(pin);
+       void __iomem *base = S3C24XX_GPIO_BASE(pin);
        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
        unsigned long flags;
        unsigned long dat;
@@ -117,78 +149,31 @@ void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
        local_irq_restore(flags);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_setpin);
+
 unsigned int s3c2410_gpio_getpin(unsigned int pin)
 {
-       unsigned long base = S3C2410_GPIO_BASE(pin);
+       void __iomem *base = S3C24XX_GPIO_BASE(pin);
        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
 
        return __raw_readl(base + 0x04) & (1<< offs);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_getpin);
+
 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
 {
        unsigned long flags;
        unsigned long misccr;
 
        local_irq_save(flags);
-       misccr = __raw_readl(S3C2410_MISCCR);
+       misccr = __raw_readl(S3C24XX_MISCCR);
        misccr &= ~clear;
        misccr ^= change;
-       __raw_writel(misccr, S3C2410_MISCCR);
+       __raw_writel(misccr, S3C24XX_MISCCR);
        local_irq_restore(flags);
 
        return misccr;
 }
 
-int s3c2410_gpio_getirq(unsigned int pin)
-{
-       if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
-               return -1;      /* not valid interrupts */
-
-       if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
-               return -1;      /* not valid pin */
-
-       if (pin < S3C2410_GPF4)
-               return (pin - S3C2410_GPF0) + IRQ_EINT0;
-
-       if (pin < S3C2410_GPG0)
-               return (pin - S3C2410_GPF4) + IRQ_EINT4;
-
-       return (pin - S3C2410_GPG0) + IRQ_EINT8;
-}
-
-int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                          unsigned int config)
-{
-       unsigned long reg = S3C2410_EINFLT0;
-       unsigned long flags;
-       unsigned long val;
-
-       if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
-               return -1;
-
-       config &= 0xff;
-
-       pin -= S3C2410_GPG8_EINT16;
-       reg += pin & ~3;
-
-       local_irq_save(flags);
-
-       /* update filter width and clock source */
-
-       val = __raw_readl(reg);
-       val &= ~(0xff << ((pin & 3) * 8));
-       val |= config << ((pin & 3) * 8);
-       __raw_writel(val, reg);
-
-       /* update filter enable */
-
-       val = __raw_readl(S3C2410_EXTINT2);
-       val &= ~(1 << ((pin * 4) + 3));
-       val |= on << ((pin * 4) + 3);
-       __raw_writel(val, S3C2410_EXTINT2);
-
-       local_irq_restore(flags);
-
-       return 0;
-}
+EXPORT_SYMBOL(s3c2410_modify_misccr);