Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff

[linux-2.6.git] / arch / arm / mm / cache-v4wb.S

diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 4f7c918..54e3c5b 100644 (file)
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -10,7 +10,7 @@
 #include <linux/config.h>
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/hardware.h>
+#include <asm/memory.h>
 #include <asm/page.h>
 #include "proc-macros.S"
 
@@ -46,6 +46,11 @@
  */
 #define CACHE_DLIMIT   (CACHE_DSIZE * 4)
 
+       .data
+flush_base:
+       .long   FLUSH_BASE
+       .text
+
 /*
  *     flush_user_cache_all()
  *
@@ -63,11 +68,21 @@ ENTRY(v4wb_flush_kern_cache_all)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 __flush_whole_cache:
-       mov     r0, #FLUSH_BASE
-       add     r1, r0, #CACHE_DSIZE
-1:     ldr     r2, [r0], #32
-       cmp     r0, r1
+       ldr     r3, =flush_base
+       ldr     r1, [r3, #0]
+       eor     r1, r1, #CACHE_DSIZE
+       str     r1, [r3, #0]
+       add     r2, r1, #CACHE_DSIZE
+1:     ldr     r3, [r1], #32
+       cmp     r1, r2
        blo     1b
+#ifdef FLUSH_BASE_MINICACHE
+       add     r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
+       sub     r1, r2, #512                    @ only 512 bytes
+1:     ldr     r3, [r1], #32
+       cmp     r1, r2
+       blo     1b
+#endif
        mcr     p15, 0, ip, c7, c10, 4          @ drain write buffer
        mov     pc, lr
 
@@ -82,6 +97,7 @@ __flush_whole_cache:
  *     - flags - vma_area_struct flags describing address space
  */
 ENTRY(v4wb_flush_user_cache_range)
+       mov     ip, #0
        sub     r3, r1, r0                      @ calculate total size
        tst     r2, #VM_EXEC                    @ executable region?
        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
@@ -121,6 +137,19 @@ ENTRY(v4wb_flush_kern_dcache_page)
  *     - end    - virtual end address
  */
 ENTRY(v4wb_coherent_kern_range)
+       /* fall through */
+
+/*
+ *     coherent_user_range(start, end)
+ *
+ *     Ensure coherency between the Icache and the Dcache in the
+ *     region described by start.  If you have non-snooping
+ *     Harvard caches, you need to implement this function.
+ *
+ *     - start  - virtual start address
+ *     - end    - virtual end address
+ */
+ENTRY(v4wb_coherent_user_range)
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
@@ -195,6 +224,7 @@ ENTRY(v4wb_cache_fns)
        .long   v4wb_flush_user_cache_all
        .long   v4wb_flush_user_cache_range
        .long   v4wb_coherent_kern_range
+       .long   v4wb_coherent_user_range
        .long   v4wb_flush_kern_dcache_page
        .long   v4wb_dma_inv_range
        .long   v4wb_dma_clean_range