Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff

[linux-2.6.git] / arch / arm / mm / cache-v6.S

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 5814f84..2c6c2a7 100644 (file)
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -18,6 +18,7 @@
 #define HARVARD_CACHE
 #define CACHE_LINE_SIZE                32
 #define D_CACHE_LINE_SIZE      32
+#define BTB_FLUSH_SIZE         8
 
 /*
  *     v6_flush_cache_all()
@@ -75,19 +76,36 @@ ENTRY(v6_flush_user_cache_range)
  *     - the Icache does not read data from the write buffer
  */
 ENTRY(v6_coherent_kern_range)
-       bic     r0, r0, #CACHE_LINE_SIZE - 1
-1:
+       /* FALLTHROUGH */
+
+/*
+ *     v6_coherent_user_range(start,end)
+ *
+ *     Ensure that the I and D caches are coherent within specified
+ *     region.  This is typically used when code has been written to
+ *     a memory region, and will be executed.
+ *
+ *     - start   - virtual start address of region
+ *     - end     - virtual end address of region
+ *
+ *     It is assumed that:
+ *     - the Icache does not read data from the write buffer
+ */
+ENTRY(v6_coherent_user_range)
+
 #ifdef HARVARD_CACHE
-       mcr     p15, 0, r0, c7, c10, 1          @ clean D line
-       mcr     p15, 0, r0, c7, c5, 1           @ invalidate I line
-#endif
-       mcr     p15, 0, r0, c7, c5, 7           @ invalidate BTB entry
+       bic     r0, r0, #CACHE_LINE_SIZE - 1
+1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D line
        add     r0, r0, #CACHE_LINE_SIZE
        cmp     r0, r1
        blo     1b
-#ifdef HARVARD_CACHE
+#endif
        mov     r0, #0
+#ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+       mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
+#else
+       mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
 #endif
        mov     pc, lr
 
@@ -151,6 +169,7 @@ ENTRY(v6_dma_inv_range)
        add     r0, r0, #D_CACHE_LINE_SIZE
        cmp     r0, r1
        blo     1b
+       mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
        mov     pc, lr
 
@@ -188,6 +207,7 @@ ENTRY(v6_dma_flush_range)
        mcr     p15, 0, r0, c7, c15, 1          @ clean & invalidate line
 #endif
        add     r0, r0, #D_CACHE_LINE_SIZE
+       cmp     r0, r1
        blo     1b
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
@@ -201,6 +221,7 @@ ENTRY(v6_cache_fns)
        .long   v6_flush_user_cache_all
        .long   v6_flush_user_cache_range
        .long   v6_coherent_kern_range
+       .long   v6_coherent_user_range
        .long   v6_flush_kern_dcache_page
        .long   v6_dma_inv_range
        .long   v6_dma_clean_range