*
* Copyright (C) 2000 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
*/
#include <linux/linkage.h>
-#include <linux/config.h>
#include <linux/init.h>
#include <asm/assembler.h>
-#include <asm/constants.h>
+#include <asm/asm-offsets.h>
+#include <asm/elf.h>
+#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
-#include <asm/procinfo.h>
#include <asm/ptrace.h>
-#include <asm/hardware.h>
+
+#include "proc-macros.S"
/*
* This is the maximum size of an area which will be invalidated
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
* - end - virtual end address
*/
ENTRY(arm1020e_coherent_kern_range)
+ /* FALLTHROUGH */
+/*
+ * coherent_user_range(start, end)
+ *
+ * Ensure coherency between the Icache and the Dcache in the
+ * region described by start. If you have non-snooping
+ * Harvard caches, you need to implement this function.
+ *
+ * - start - virtual start address
+ * - end - virtual end address
+ */
+ENTRY(arm1020e_coherent_user_range)
mov ip, #0
bic r0, r0, #CACHE_DLINESIZE - 1
1:
.long arm1020e_flush_user_cache_all
.long arm1020e_flush_user_cache_range
.long arm1020e_coherent_kern_range
+ .long arm1020e_coherent_user_range
.long arm1020e_flush_kern_dcache_page
.long arm1020e_dma_inv_range
.long arm1020e_dma_clean_range
*/
.align 5
ENTRY(cpu_arm1020e_switch_mm)
+#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r3, c7, c10, 4
mov r1, #0xF @ 16 segments
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
* Set a PTE and flush it out
*/
.align 5
-ENTRY(cpu_arm1020e_set_pte)
+ENTRY(cpu_arm1020e_set_pte_ext)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
+#endif /* CONFIG_MMU */
mov pc, lr
__INIT
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
- mcr p15, 0, r4, c2, c0 @ load page table pointer
- mov r0, #0x1f @ Domains 0, 1 = client
- mcr p15, 0, r0, c3, c0 @ load domain access register
+#endif
+ adr r5, arm1020e_crval
+ ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4
-/*
- * Clear out 'unwanted' bits (then put them in if we need them)
- */
- bic r0, r0, #0x1e00 @ i...??r.........
- bic r0, r0, #0x000e @ ............wca.
-/*
- * Turn on what we want
- */
- orr r0, r0, #0x0031 @ ..........DP...M
- orr r0, r0, #0x0100 @ .......S........
-
+ bic r0, r0, r5
+ orr r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
- orr r0, r0, #0x4000 @ .R..............
-#endif
-#ifndef CONFIG_CPU_BPREDICT_DISABLE
- orr r0, r0, #0x0800 @ ....Z...........
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
- orr r0, r0, #0x0004 @ Enable D cache
-#endif
-#ifndef CONFIG_CPU_ICACHE_DISABLE
- orr r0, r0, #0x1000 @ I Cache on
+ orr r0, r0, #0x4000 @ .R.. .... .... ....
#endif
mov pc, lr
.size __arm1020e_setup, . - __arm1020e_setup
+ /*
+ * R
+ * .RVI ZFRS BLDP WCAM
+ * .011 1001 ..11 0101
+ */
+ .type arm1020e_crval, #object
+arm1020e_crval:
+ crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
+
__INITDATA
/*
.word cpu_arm1020e_do_idle
.word cpu_arm1020e_dcache_clean_area
.word cpu_arm1020e_switch_mm
- .word cpu_arm1020e_set_pte
+ .word cpu_arm1020e_set_pte_ext
.size arm1020e_processor_functions, . - arm1020e_processor_functions
.section ".rodata"
.type cpu_arm1020e_name, #object
cpu_arm1020e_name:
- .ascii "ARM1020E"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
- .ascii "i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
- .ascii "d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
- .ascii "(wt)"
-#else
- .ascii "(wb)"
-#endif
-#endif
-#ifndef CONFIG_CPU_BPREDICT_DISABLE
- .ascii "B"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
- .ascii "RR"
-#endif
- .ascii "\0"
+ .asciz "ARM1020E"
.size cpu_arm1020e_name, . - cpu_arm1020e_name
.align
- .section ".proc.info", #alloc, #execinstr
+ .section ".proc.info.init", #alloc, #execinstr
.type __arm1020e_proc_info,#object
__arm1020e_proc_info:
.long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
.long 0xff0ffff0
- .long 0x00000c12 @ mmuflags
+ .long PMD_TYPE_SECT | \
+ PMD_BIT4 | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
+ .long PMD_TYPE_SECT | \
+ PMD_BIT4 | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
b __arm1020e_setup
.long cpu_arch_name
.long cpu_elf_name
- .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
+ .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
.long cpu_arm1020e_name
.long arm1020e_processor_functions
.long v4wbi_tlb_fns
git://git.onelab.eu / linux-2.6.git / blobdiff