Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff

[linux-2.6.git] / arch / arm / mm / proc-arm1020e.S

diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 0332c3e..be6d081 100644 (file)
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -28,11 +28,11 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/constants.h>
+#include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
-#include <asm/hardware.h>
 
 /*
  * This is the maximum size of an area which will be invalidated
@@ -193,6 +193,18 @@ ENTRY(arm1020e_flush_user_cache_range)
  *     - end   - virtual end address
  */
 ENTRY(arm1020e_coherent_kern_range)
+       /* FALLTHROUGH */
+/*
+ *     coherent_user_range(start, end)
+ *
+ *     Ensure coherency between the Icache and the Dcache in the
+ *     region described by start.  If you have non-snooping
+ *     Harvard caches, you need to implement this function.
+ *
+ *     - start - virtual start address
+ *     - end   - virtual end address
+ */
+ENTRY(arm1020e_coherent_user_range)
        mov     ip, #0
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:
@@ -304,6 +316,7 @@ ENTRY(arm1020e_cache_fns)
        .long   arm1020e_flush_user_cache_all
        .long   arm1020e_flush_user_cache_range
        .long   arm1020e_coherent_kern_range
+       .long   arm1020e_coherent_user_range
        .long   arm1020e_flush_kern_dcache_page
        .long   arm1020e_dma_inv_range
        .long   arm1020e_dma_clean_range
@@ -400,36 +413,29 @@ __arm1020e_setup:
        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
-       mcr     p15, 0, r4, c2, c0              @ load page table pointer
-       mov     r0, #0x1f                       @ Domains 0, 1 = client
-       mcr     p15, 0, r0, c3, c0              @ load domain access register
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-/*
- * Clear out 'unwanted' bits (then put them in if we need them)
- */
-       bic     r0, r0, #0x1e00                 @ i...??r.........
-       bic     r0, r0, #0x000e                 @ ............wca.
-/*
- * Turn on what we want
- */
-       orr     r0, r0, #0x0031                 @ ..........DP...M
-       orr     r0, r0, #0x0100                 @ .......S........
-
+       ldr     r5, arm1020e_cr1_clear
+       bic     r0, r0, r5
+       ldr     r5, arm1020e_cr1_set
+       orr     r0, r0, r5
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-       orr     r0, r0, #0x4000                 @ .R..............
-#endif
-#ifndef CONFIG_CPU_BPREDICT_DISABLE
-       orr     r0, r0, #0x0800                 @ ....Z...........
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-       orr     r0, r0, #0x0004                 @ Enable D cache
-#endif
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-       orr     r0, r0, #0x1000                 @ I Cache on
+       orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 #endif
        mov     pc, lr
        .size   __arm1020e_setup, . - __arm1020e_setup
 
+       /*
+        *  R
+        * .RVI ZFRS BLDP WCAM
+        * .011 1001 ..11 0101
+        */
+       .type   arm1020e_cr1_clear, #object
+       .type   arm1020e_cr1_set, #object
+arm1020e_cr1_clear:
+       .word   0x5f3f
+arm1020e_cr1_set:
+       .word   0x3935
+
        __INITDATA
 
 /*
@@ -485,17 +491,20 @@ cpu_arm1020e_name:
 
        .align
 
-       .section ".proc.info", #alloc, #execinstr
+       .section ".proc.info.init", #alloc, #execinstr
 
        .type   __arm1020e_proc_info,#object
 __arm1020e_proc_info:
        .long   0x4105a200                      @ ARM 1020TE (Architecture v5TE)
        .long   0xff0ffff0
-       .long   0x00000c12                      @ mmuflags
+       .long   PMD_TYPE_SECT | \
+               PMD_BIT4 | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
        b       __arm1020e_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
-       .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
+       .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
        .long   cpu_arm1020e_name
        .long   arm1020e_processor_functions
        .long   v4wbi_tlb_fns