Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff

[linux-2.6.git] / arch / arm / mm / proc-arm922.S

diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 8606511..bbde4a0 100644 (file)
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,9 +29,9 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
-#include <asm/hardware.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"
@@ -184,6 +184,19 @@ ENTRY(arm922_flush_user_cache_range)
  *     - end   - virtual end address
  */
 ENTRY(arm922_coherent_kern_range)
+       /* FALLTHROUGH */
+
+/*
+ *     coherent_user_range(start, end)
+ *
+ *     Ensure coherency between the Icache and the Dcache in the
+ *     region described by start, end.  If you have non-snooping
+ *     Harvard caches, you need to implement this function.
+ *
+ *     - start - virtual start address
+ *     - end   - virtual end address
+ */
+ENTRY(arm922_coherent_user_range)
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
@@ -279,6 +292,7 @@ ENTRY(arm922_cache_fns)
        .long   arm922_flush_user_cache_all
        .long   arm922_flush_user_cache_range
        .long   arm922_coherent_kern_range
+       .long   arm922_coherent_user_range
        .long   arm922_flush_kern_dcache_page
        .long   arm922_dma_inv_range
        .long   arm922_dma_clean_range
@@ -372,33 +386,27 @@ __arm922_setup:
        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
-       mcr     p15, 0, r4, c2, c0              @ load page table pointer
-       mov     r0, #0x1f                       @ Domains 0, 1 = client
-       mcr     p15, 0, r0, c3, c0              @ load domain access register
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-/*
- * Clear out 'unwanted' bits (then put them in if we need them)
- */
-                                               @   VI ZFRS BLDP WCAM
-       bic     r0, r0, #0x0e00
-       bic     r0, r0, #0x0002
-       bic     r0, r0, #0x000c
-       bic     r0, r0, #0x1000                 @ ...0 000. .... 000.
-/*
- * Turn on what we want
- */
-       orr     r0, r0, #0x0031
-       orr     r0, r0, #0x2100                 @ ..1. ...1 ..11 ...1
-
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-       orr     r0, r0, #0x0004                 @ .... .... .... .1..
-#endif
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-       orr     r0, r0, #0x1000                 @ ...1 .... .... ....
-#endif
+       ldr     r5, arm922_cr1_clear
+       bic     r0, r0, r5
+       ldr     r5, arm922_cr1_set
+       orr     r0, r0, r5
        mov     pc, lr
        .size   __arm922_setup, . - __arm922_setup
 
+       /*
+        *  R
+        * .RVI ZFRS BLDP WCAM
+        * ..11 0001 ..11 0101
+        * 
+        */
+       .type   arm922_cr1_clear, #object
+       .type   arm922_cr1_set, #object
+arm922_cr1_clear:
+       .word   0x3f3f
+arm922_cr1_set:
+       .word   0x3135
+
        __INITDATA
 
 /*
@@ -448,13 +456,18 @@ cpu_arm922_name:
 
        .align
 
-       .section ".proc.info", #alloc, #execinstr
+       .section ".proc.info.init", #alloc, #execinstr
 
        .type   __arm922_proc_info,#object
 __arm922_proc_info:
        .long   0x41009220
        .long   0xff00fff0
-       .long   0x00000c1e                      @ mmuflags
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_BIT4 | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
        b       __arm922_setup
        .long   cpu_arch_name
        .long   cpu_elf_name