Revert to Fedora kernel-2.6.17-1.2187_FC5 patched with vs2.0.2.1; there are too many...

[linux-2.6.git] / arch / arm / mm / proc-sa110.S

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index d58fce5..a2dd5ae 100644 (file)
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -15,9 +15,10 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/constants.h>
+#include <asm/asm-offsets.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
@@ -25,22 +26,7 @@
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE 32
-#define FLUSH_OFFSET   32768
 
-       .macro flush_110_dcache rd, ra, re
-       ldr     \rd, =flush_base
-       ldr     \ra, [\rd]
-       eor     \ra, \ra, #FLUSH_OFFSET
-       str     \ra, [\rd]
-       add     \re, \ra, #16384                @ only necessary for 16k
-1001:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1001b
-       .endm
-
-       .data
-flush_base:
-       .long   FLUSH_BASE
        .text
 
 /*
@@ -144,13 +130,11 @@ ENTRY(cpu_sa110_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_sa110_switch_mm)
-       flush_110_dcache        r3, ip, r1
-       mov     r1, #0
-       mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
-       mcr     p15, 0, r1, c7, c10, 4          @ drain WB
+       str     lr, [sp, #-4]!
+       bl      v4wb_flush_kern_cache_all       @ clears IP
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
-       mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
-       mov     pc, lr
+       mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+       ldr     pc, [sp], #4
 
 /*
  * cpu_sa110_set_pte(ptep, pte)
@@ -186,21 +170,31 @@ ENTRY(cpu_sa110_set_pte)
 
        .type   __sa110_setup, #function
 __sa110_setup:
-       mrc     p15, 0, r0, c1, c0              @ get control register v4
-       bic     r0, r0, #0x2e00                 @ ..VI ZFRS BLDP WCAM
-       bic     r0, r0, #0x0002                 @ ..0. 000. .... ..0.
-       orr     r0, r0, #0x003d
-       orr     r0, r0, #0x1100                 @ ...1 ...1 ..11 11.1
        mov     r10, #0
        mcr     p15, 0, r10, c7, c7             @ invalidate I,D caches on v4
        mcr     p15, 0, r10, c7, c10, 4         @ drain write buffer on v4
        mcr     p15, 0, r10, c8, c7             @ invalidate I,D TLBs on v4
-       mcr     p15, 0, r4, c2, c0              @ load page table pointer
-       mov     r10, #0x1f                      @ Domains 0, 1 = client
-       mcr     p15, 0, r10, c3, c0             @ load domain access register
+       mrc     p15, 0, r0, c1, c0              @ get control register v4
+       ldr     r5, sa110_cr1_clear
+       bic     r0, r0, r5
+       ldr     r5, sa110_cr1_set
+       orr     r0, r0, r5
        mov     pc, lr
        .size   __sa110_setup, . - __sa110_setup
 
+       /*
+        *  R
+        * .RVI ZFRS BLDP WCAM
+        * ..01 0001 ..11 1101
+        * 
+        */
+       .type   sa110_cr1_clear, #object
+       .type   sa110_cr1_set, #object
+sa110_cr1_clear:
+       .word   0x3f3f
+sa110_cr1_set:
+       .word   0x113d
+
        __INITDATA
 
 /*
@@ -239,13 +233,17 @@ cpu_sa110_name:
 
        .align
 
-       .section ".proc.info", #alloc, #execinstr
+       .section ".proc.info.init", #alloc, #execinstr
 
        .type   __sa110_proc_info,#object
 __sa110_proc_info:
        .long   0x4401a100
        .long   0xfffffff0
-       .long   0x00000c0e
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
        b       __sa110_setup
        .long   cpu_arch_name
        .long   cpu_elf_name