Revert to Fedora kernel-2.6.17-1.2187_FC5 patched with vs2.0.2.1; there are too many...

[linux-2.6.git] / arch / arm / mm / proc-sa1100.S

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 5d444e4..777ad99 100644 (file)
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -20,39 +20,16 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/constants.h>
+#include <asm/asm-offsets.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
 /*
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE 32
-#define FLUSH_OFFSET   32768
-
-       .macro flush_1100_dcache rd, ra, re
-       ldr     \rd, =flush_base
-       ldr     \ra, [\rd]
-       eor     \ra, \ra, #FLUSH_OFFSET
-       str     \ra, [\rd]
-       add     \re, \ra, #8192                 @ only necessary for 8k
-1001:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1001b
-#ifdef FLUSH_BASE_MINICACHE
-       add     \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
-       add     \re, \ra, #512                  @ only 512 bytes
-1002:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1002b
-#endif
-       .endm
-
-       .data
-flush_base:
-       .long   FLUSH_BASE
-       .text
 
        __INIT
 
@@ -78,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin)
        stmfd   sp!, {lr}
        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
        msr     cpsr_c, ip
-       flush_1100_dcache r0, r1, r2            @ clean caches
-       mov     r0, #0
-       mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
+       bl      v4wb_flush_kern_cache_all
+       mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
@@ -166,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_sa1100_switch_mm)
-       flush_1100_dcache r3, ip, r1
-       mov     ip, #0
-       mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+       str     lr, [sp, #-4]!
+       bl      v4wb_flush_kern_cache_all       @ clears IP
        mcr     p15, 0, ip, c9, c0, 0           @ invalidate RB
-       mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-       mov     pc, lr
+       ldr     pc, [sp], #4
 
 /*
  * cpu_sa1100_set_pte(ptep, pte)
@@ -209,21 +183,31 @@ ENTRY(cpu_sa1100_set_pte)
 
        .type   __sa1100_setup, #function
 __sa1100_setup:
-       mov     r10, #0
-       mcr     p15, 0, r10, c7, c7             @ invalidate I,D caches on v4
-       mcr     p15, 0, r10, c7, c10, 4         @ drain write buffer on v4
-       mcr     p15, 0, r10, c8, c7             @ invalidate I,D TLBs on v4
-       mov     r0, #0x1f                       @ Domains 0, 1 = client
-       mcr     p15, 0, r0, c3, c0              @ load domain access register
-       mcr     p15, 0, r4, c2, c0              @ load page table pointer
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
+       mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
+       mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       bic     r0, r0, #0x0e00                 @ ..VI ZFRS BLDP WCAM
-       bic     r0, r0, #0x0002                 @ .... 000. .... ..0.
-       orr     r0, r0, #0x003d
-       orr     r0, r0, #0x3100                 @ ..11 ...1 ..11 11.1
+       ldr     r5, sa1100_cr1_clear
+       bic     r0, r0, r5
+       ldr     r5, sa1100_cr1_set
+       orr     r0, r0, r5
        mov     pc, lr
        .size   __sa1100_setup, . - __sa1100_setup
 
+       /*
+        *  R
+        * .RVI ZFRS BLDP WCAM
+        * ..11 0001 ..11 1101
+        * 
+        */
+       .type   sa1100_cr1_clear, #object
+       .type   sa1100_cr1_set, #object
+sa1100_cr1_clear:
+       .word   0x3f3f
+sa1100_cr1_set:
+       .word   0x313d
+
        __INITDATA
 
 /*
@@ -270,13 +254,17 @@ cpu_sa1110_name:
 
        .align
 
-       .section ".proc.info", #alloc, #execinstr
+       .section ".proc.info.init", #alloc, #execinstr
 
        .type   __sa1100_proc_info,#object
 __sa1100_proc_info:
        .long   0x4401a110
        .long   0xfffffff0
-       .long   0x00000c0e
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
        b       __sa1100_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@ -292,7 +280,11 @@ __sa1100_proc_info:
 __sa1110_proc_info:
        .long   0x6901b110
        .long   0xfffffff0
-       .long   0x00000c0e
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
        b       __sa1100_setup
        .long   cpu_arch_name
        .long   cpu_elf_name