s64 d = vfp_double_pack(vd);
pr_debug("VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func,
dd, d, exceptions);
- vfp_put_double(d, dd);
+ vfp_put_double(dd, d);
}
return exceptions;
}
*/
static u32 vfp_double_fabs(int dd, int unused, int dm, u32 fpscr)
{
- vfp_put_double(vfp_double_packed_abs(vfp_get_double(dm)), dd);
+ vfp_put_double(dd, vfp_double_packed_abs(vfp_get_double(dm)));
return 0;
}
static u32 vfp_double_fcpy(int dd, int unused, int dm, u32 fpscr)
{
- vfp_put_double(vfp_get_double(dm), dd);
+ vfp_put_double(dd, vfp_get_double(dm));
return 0;
}
static u32 vfp_double_fneg(int dd, int unused, int dm, u32 fpscr)
{
- vfp_put_double(vfp_double_packed_negate(vfp_get_double(dm)), dd);
+ vfp_put_double(dd, vfp_double_packed_negate(vfp_get_double(dm)));
return 0;
}
vdp = &vfp_double_default_qnan;
ret = FPSCR_IOC;
}
- vfp_put_double(vfp_double_pack(vdp), dd);
+ vfp_put_double(dd, vfp_double_pack(vdp));
return ret;
}
*/
if (tm & (VFP_INFINITY|VFP_NAN)) {
vsd.exponent = 255;
- if (tm == VFP_QNAN)
+ if (tm & VFP_NAN)
vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN;
goto pack_nan;
} else if (tm & VFP_ZERO)
return vfp_single_normaliseround(sd, &vsd, fpscr, exceptions, "fcvts");
pack_nan:
- vfp_put_float(vfp_single_pack(&vsd), sd);
+ vfp_put_float(sd, vfp_single_pack(&vsd));
return exceptions;
}
pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
- vfp_put_float(d, sd);
+ vfp_put_float(sd, d);
return exceptions;
}
pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
- vfp_put_float((s32)d, sd);
+ vfp_put_float(sd, (s32)d);
return exceptions;
}
vdn_nan:
exceptions = vfp_propagate_nan(&vdd, &vdn, &vdm, fpscr);
pack:
- vfp_put_double(vfp_double_pack(&vdd), dd);
+ vfp_put_double(dd, vfp_double_pack(&vdd));
return exceptions;
vdm_nan:
goto pack;
invalid:
- vfp_put_double(vfp_double_pack(&vfp_double_default_qnan), dd);
+ vfp_put_double(dd, vfp_double_pack(&vfp_double_default_qnan));
return FPSCR_IOC;
}
{
u32 op = inst & FOP_MASK;
u32 exceptions = 0;
- unsigned int dest;
+ unsigned int dd = vfp_get_dd(inst);
unsigned int dn = vfp_get_dn(inst);
unsigned int dm = vfp_get_dm(inst);
unsigned int vecitr, veclen, vecstride;
veclen = fpscr & FPSCR_LENGTH_MASK;
vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;
- /*
- * fcvtds takes an sN register number as destination, not dN.
- * It also always operates on scalars.
- */
- if ((inst & FEXT_MASK) == FEXT_FCVT) {
- veclen = 0;
- dest = vfp_get_sd(inst);
- } else
- dest = vfp_get_dd(inst);
-
/*
* If destination bank is zero, vector length is always '1'.
* ARM DDI0100F C5.1.3, C5.3.2.
*/
- if (FREG_BANK(dest) == 0)
+ if (FREG_BANK(dd) == 0)
veclen = 0;
pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
u32 except;
- if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)
- pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n",
- vecitr >> FPSCR_LENGTH_BIT,
- dest, dn, dm);
- else if (op == FOP_EXT)
+ if (op == FOP_EXT)
pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",
vecitr >> FPSCR_LENGTH_BIT,
- dest, dn, dm);
+ dd, dn, dm);
else
pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n",
vecitr >> FPSCR_LENGTH_BIT,
- dest, dn, FOP_TO_IDX(op), dm);
+ dd, dn, FOP_TO_IDX(op), dm);
- except = fop(dest, dn, dm, fpscr);
+ except = fop(dd, dn, dm, fpscr);
pr_debug("VFP: itr%d: exceptions=%08x\n",
vecitr >> FPSCR_LENGTH_BIT, except);
* we encounter an exception. We continue.
*/
- dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);
+ dd = FREG_BANK(dd) + ((FREG_IDX(dd) + vecstride) & 6);
dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);
if (FREG_BANK(dm) != 0)
dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6);