linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / i386 / kernel / cpu / cpufreq / cpufreq-nforce2.c

diff --git a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
index f275e0d..2b62dee 100644 (file)
--- a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
@@ -39,7 +39,7 @@ static struct pci_dev *nforce2_chipset_dev;
 static int fid = 0;
 
 /* min_fsb, max_fsb:
- * minimum and maximum FSB (= FSB at boot time)
+ * minimum and maximum FSB (= FSB at boot time) 
  */
 static int min_fsb = 0;
 static int max_fsb = 0;
@@ -57,10 +57,10 @@ MODULE_PARM_DESC(min_fsb,
 
 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
 
-/**
+/*
  * nforce2_calc_fsb - calculate FSB
  * @pll: PLL value
- *
+ * 
  *   Calculates FSB from PLL value
  */
 static int nforce2_calc_fsb(int pll)
@@ -76,10 +76,10 @@ static int nforce2_calc_fsb(int pll)
        return 0;
 }
 
-/**
+/*
  * nforce2_calc_pll - calculate PLL value
  * @fsb: FSB
- *
+ * 
  *   Calculate PLL value for given FSB
  */
 static int nforce2_calc_pll(unsigned int fsb)
@@ -106,10 +106,10 @@ static int nforce2_calc_pll(unsigned int fsb)
        return NFORCE2_PLL(mul, div);
 }
 
-/**
+/*
  * nforce2_write_pll - write PLL value to chipset
  * @pll: PLL value
- *
+ * 
  *   Writes new FSB PLL value to chipset
  */
 static void nforce2_write_pll(int pll)
@@ -121,13 +121,15 @@ static void nforce2_write_pll(int pll)
        pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
 
        /* Now write the value in all 64 registers */
-       for (temp = 0; temp <= 0x3f; temp++)
-               pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
+       for (temp = 0; temp <= 0x3f; temp++) {
+               pci_write_config_dword(nforce2_chipset_dev, 
+                                       NFORCE2_PLLREG, pll);
+       }
 
        return;
 }
 
-/**
+/*
  * nforce2_fsb_read - Read FSB
  *
  *   Read FSB from chipset
@@ -138,32 +140,39 @@ static unsigned int nforce2_fsb_read(int bootfsb)
        struct pci_dev *nforce2_sub5;
        u32 fsb, temp = 0;
 
+       
        /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
        nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
-                                               0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
+                                      0x01EF,
+                                      PCI_ANY_ID,
+                                      PCI_ANY_ID,
+                                      NULL);
+       
        if (!nforce2_sub5)
                return 0;
 
        pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
        fsb /= 1000000;
-
+       
        /* Check if PLL register is already set */
-       pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
-
+       pci_read_config_byte(nforce2_chipset_dev, 
+                             NFORCE2_PLLENABLE, (u8 *)&temp);
+       
        if(bootfsb || !temp)
                return fsb;
                
        /* Use PLL register FSB value */
-       pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
+       pci_read_config_dword(nforce2_chipset_dev, 
+                              NFORCE2_PLLREG, &temp);
        fsb = nforce2_calc_fsb(temp);
 
        return fsb;
 }
 
-/**
+/*
  * nforce2_set_fsb - set new FSB
  * @fsb: New FSB
- *
+ * 
  *   Sets new FSB
  */
 static int nforce2_set_fsb(unsigned int fsb)
@@ -177,7 +186,7 @@ static int nforce2_set_fsb(unsigned int fsb)
                printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
                return -EINVAL;
        }
-
+       
        tfsb = nforce2_fsb_read(0);
        if (!tfsb) {
                printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
@@ -185,7 +194,8 @@ static int nforce2_set_fsb(unsigned int fsb)
        }
 
        /* First write? Then set actual value */
-       pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
+       pci_read_config_byte(nforce2_chipset_dev, 
+                             NFORCE2_PLLENABLE, (u8 *)&temp);
        if (!temp) {
                pll = nforce2_calc_pll(tfsb);
 
@@ -213,7 +223,7 @@ static int nforce2_set_fsb(unsigned int fsb)
                /* Calculate the PLL reg. value */
                if ((pll = nforce2_calc_pll(tfsb)) == -1)
                        return -EINVAL;
-
+               
                nforce2_write_pll(pll);
 #ifdef NFORCE2_DELAY
                mdelay(NFORCE2_DELAY);
@@ -229,7 +239,7 @@ static int nforce2_set_fsb(unsigned int fsb)
 /**
  * nforce2_get - get the CPU frequency
  * @cpu: CPU number
- *
+ * 
  * Returns the CPU frequency
  */
 static unsigned int nforce2_get(unsigned int cpu)
@@ -344,10 +354,10 @@ static int nforce2_cpu_init(struct cpufreq_policy *policy)
 
        printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
               fid / 10, fid % 10);
-
+       
        /* Set maximum FSB to FSB at boot time */
        max_fsb = nforce2_fsb_read(1);
-
+       
        if(!max_fsb)
                return -EIO;
 
@@ -388,15 +398,17 @@ static struct cpufreq_driver nforce2_driver = {
  * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
  *
  * Detects nForce2 A2 and C1 stepping
- *
+ * 
  */
 static unsigned int nforce2_detect_chipset(void)
 {
        u8 revision;
 
        nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
-                                       PCI_DEVICE_ID_NVIDIA_NFORCE2,
-                                       PCI_ANY_ID, PCI_ANY_ID, NULL);
+                                             PCI_DEVICE_ID_NVIDIA_NFORCE2,
+                                             PCI_ANY_ID,
+                                             PCI_ANY_ID,
+                                             NULL);
 
        if (nforce2_chipset_dev == NULL)
                return -ENODEV;