* The author(s) of this software shall not be held liable for damages
* of any nature resulting due to the use of this software. This
* software is provided AS-IS with no warranties.
- *
+ *
* Date Errata Description
* 20020525 N44, O17 12.5% or 25% DC causes lockup
*
#include <linux/config.h>
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/cpumask.h>
+#include <linux/sched.h> /* current / set_cpus_allowed() */
-#include <asm/processor.h>
+#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/timex.h>
#include "speedstep-lib.h"
#define PFX "p4-clockmod: "
+#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "p4-clockmod", msg)
/*
* Duty Cycle (3bits), note DC_DISABLE is not specified in
static int has_N44_O17_errata[NR_CPUS];
+static int has_N60_errata[NR_CPUS];
static unsigned int stock_freq;
static struct cpufreq_driver p4clockmod_driver;
static unsigned int cpufreq_p4_get(unsigned int cpu);
return -EINVAL;
rdmsr(MSR_IA32_THERM_STATUS, l, h);
-#if 0
+
if (l & 0x01)
- printk(KERN_DEBUG PFX "CPU#%d currently thermal throttled\n", cpu);
-#endif
+ dprintk("CPU#%d currently thermal throttled\n", cpu);
+
if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT))
newstate = DC_38PT;
rdmsr(MSR_IA32_THERM_CONTROL, l, h);
if (newstate == DC_DISABLE) {
- /* printk(KERN_INFO PFX "CPU#%d disabling modulation\n", cpu); */
+ dprintk("CPU#%d disabling modulation\n", cpu);
wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
} else {
- /* printk(KERN_INFO PFX "CPU#%d setting duty cycle to %d%%\n",
- cpu, ((125 * newstate) / 10)); */
- /* bits 63 - 5 : reserved
+ dprintk("CPU#%d setting duty cycle to %d%%\n",
+ cpu, ((125 * newstate) / 10));
+ /* bits 63 - 5 : reserved
* bit 4 : enable/disable
* bits 3-1 : duty cycle
* bit 0 : reserved
{
unsigned int newstate = DC_RESV;
struct cpufreq_freqs freqs;
- cpumask_t cpus_allowed, affected_cpu_map;
+ cpumask_t cpus_allowed;
int i;
if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
if (freqs.new == freqs.old)
return 0;
- /* switch to physical CPU where state is to be changed*/
- cpus_allowed = current->cpus_allowed;
-
- /* only run on CPU to be set, or on its sibling */
-#ifdef CONFIG_SMP
- affected_cpu_map = cpu_sibling_map[policy->cpu];
-#else
- affected_cpu_map = cpumask_of_cpu(policy->cpu);
-#endif
-
/* notifiers */
- for_each_cpu_mask(i, affected_cpu_map) {
+ for_each_cpu_mask(i, policy->cpus) {
freqs.cpu = i;
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
}
/* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
- * Developer's Manual, Volume 3
+ * Developer's Manual, Volume 3
*/
- for_each_cpu_mask(i, affected_cpu_map) {
+ cpus_allowed = current->cpus_allowed;
+
+ for_each_cpu_mask(i, policy->cpus) {
cpumask_t this_cpu = cpumask_of_cpu(i);
set_cpus_allowed(current, this_cpu);
set_cpus_allowed(current, cpus_allowed);
/* notifiers */
- for_each_cpu_mask(i, affected_cpu_map) {
+ for_each_cpu_mask(i, policy->cpus) {
freqs.cpu = i;
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
}
return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
}
- if ((c->x86 == 0x06) && (c->x86_model == 0x13)) {
+ if ((c->x86 == 0x06) && (c->x86_model == 0x0D)) {
/* Pentium M (Dothan) */
printk(KERN_WARNING PFX "Warning: Pentium M detected. "
"The speedstep_centrino module offers voltage scaling"
return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
}
-
+
static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
{
int cpuid = 0;
unsigned int i;
+#ifdef CONFIG_SMP
+ policy->cpus = cpu_sibling_map[policy->cpu];
+#endif
+
/* Errata workaround */
cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
switch (cpuid) {
case 0x0f11:
case 0x0f12:
has_N44_O17_errata[policy->cpu] = 1;
+ dprintk("has errata -- disabling low frequencies\n");
+ break;
+
+ case 0x0f29:
+ has_N60_errata[policy->cpu] = 1;
+ dprintk("has errata -- disabling frequencies lower than 2ghz\n");
+ break;
}
-
+
/* get max frequency */
stock_freq = cpufreq_p4_get_frequency(c);
if (!stock_freq)
for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
if ((i<2) && (has_N44_O17_errata[policy->cpu]))
p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
+ else if (has_N60_errata[policy->cpu] && ((stock_freq * i)/8) < 2000000)
+ p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
else
p4clockmod_table[i].frequency = (stock_freq * i)/8;
}
cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
-
+
/* cpuinfo and default policy values */
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
policy->cpuinfo.transition_latency = 1000000; /* assumed */
static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
{
- cpufreq_frequency_table_put_attr(policy->cpu);
+ cpufreq_frequency_table_put_attr(policy->cpu);
return 0;
}
static unsigned int cpufreq_p4_get(unsigned int cpu)
{
- cpumask_t cpus_allowed, affected_cpu_map;
+ cpumask_t cpus_allowed;
u32 l, h;
cpus_allowed = current->cpus_allowed;
- affected_cpu_map = cpumask_of_cpu(cpu);
- set_cpus_allowed(current, affected_cpu_map);
- BUG_ON(!cpu_isset(smp_processor_id(), affected_cpu_map));
+ set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ BUG_ON(smp_processor_id() != cpu);
rdmsr(MSR_IA32_THERM_CONTROL, l, h);
};
static struct cpufreq_driver p4clockmod_driver = {
- .verify = cpufreq_p4_verify,
+ .verify = cpufreq_p4_verify,
.target = cpufreq_p4_target,
.init = cpufreq_p4_cpu_init,
.exit = cpufreq_p4_cpu_exit,
static int __init cpufreq_p4_init(void)
-{
+{
struct cpuinfo_x86 *c = cpu_data;
+ int ret;
/*
- * THERM_CONTROL is architectural for IA32 now, so
+ * THERM_CONTROL is architectural for IA32 now, so
* we can rely on the capability checks
*/
if (c->x86_vendor != X86_VENDOR_INTEL)
!test_bit(X86_FEATURE_ACC, c->x86_capability))
return -ENODEV;
- printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
+ ret = cpufreq_register_driver(&p4clockmod_driver);
+ if (!ret)
+ printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
- return cpufreq_register_driver(&p4clockmod_driver);
+ return (ret);
}
late_initcall(cpufreq_p4_init);
module_exit(cpufreq_p4_exit);
-
git://git.onelab.eu / linux-2.6.git / blobdiff