#include <asm/desc.h>
#include <asm/voyager.h>
#include <asm/vic.h>
-#include <asm/pgalloc.h>
#include <asm/mtrr.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
-#include <asm/desc.h>
#include <asm/arch_hooks.h>
#include <linux/irq.h>
-int reboot_smp = 0;
-
/* TLB state -- visible externally, indexed physically */
-struct tlb_state cpu_tlbstate[NR_CPUS] __cacheline_aligned = {[0 ... NR_CPUS-1] = { &init_mm, 0 }};
+DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
/* CPU IRQ affinity -- set to all ones initially */
static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
send_CPI_allbutself(__u8 cpi)
{
__u8 cpu = smp_processor_id();
- __u32 mask = cpus_coerce(cpu_online_map) & ~(1 << cpu);
+ __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
send_CPI(mask, cpi);
}
static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
/* Lock for enable/disable of VIC interrupts */
-static spinlock_t vic_irq_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
+static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
/* The boot processor is correctly set up in PC mode when it
* comes up, but the secondaries need their master/slave 8259
/* set up everything for just this CPU, we can alter
* this as we start the other CPUs later */
/* now get the CPU disposition from the extended CMOS */
- phys_cpu_present_map = cpus_promote(voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK));
- cpus_coerce(phys_cpu_present_map) |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
- cpus_coerce(phys_cpu_present_map) |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
- cpus_coerce(phys_cpu_present_map) |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
- printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_coerce(phys_cpu_present_map));
+ cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
+ cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
+ cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
+ cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
+ printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
/* Here we set up the VIC to enable SMP */
/* enable the CPIs by writing the base vector to their register */
outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
}
/* Routine initially called when a non-boot CPU is brought online */
-int __init
+static void __init
start_secondary(void *unused)
{
__u8 cpuid = hard_smp_processor_id();
/* external functions not defined in the headers */
extern void calibrate_delay(void);
- extern int cpu_idle(void);
cpu_init();
cpu_set(cpuid, cpu_online_map);
wmb();
- return cpu_idle();
-}
-
-static struct task_struct * __init
-fork_by_hand(void)
-{
- struct pt_regs regs;
- /* don't care about the eip and regs settings since we'll
- * never reschedule the forked task. */
- return copy_process(CLONE_VM|CLONE_IDLETASK, 0, ®s, 0, NULL, NULL);
+ cpu_idle();
}
hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
cpucount++;
- idle = fork_by_hand();
+ idle = fork_idle(cpu);
if(IS_ERR(idle))
panic("failed fork for CPU%d", cpu);
-
- wake_up_forked_process(idle);
-
- init_idle(idle, cpu);
-
idle->thread.eip = (unsigned long) start_secondary;
- unhash_process(idle);
/* init_tasks (in sched.c) is indexed logically */
stack_start.esp = (void *) idle->thread.esp;
/* now that the cat has probed the Voyager System Bus, sanity
* check the cpu map */
if( ((voyager_quad_processors | voyager_extended_vic_processors)
- & cpus_coerce(phys_cpu_present_map)) != cpus_coerce(phys_cpu_present_map)) {
+ & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
/* should panic */
printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
}
} else if(voyager_level == 4)
- voyager_extended_vic_processors = cpus_coerce(phys_cpu_present_map);
+ voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
/* this sets up the idle task to run on the current cpu */
voyager_extended_cpus = 1;
* System interrupts occur because some problem was detected on the
* various busses. To find out what you have to probe all the
* hardware via the CAT bus. FIXME: At the moment we do nothing. */
-asmlinkage void
-smp_vic_sys_interrupt(void)
+fastcall void
+smp_vic_sys_interrupt(struct pt_regs *regs)
{
ack_CPI(VIC_SYS_INT);
printk("Voyager SYSTEM INTERRUPT\n");
/* Handle a voyager CMN_INT; These interrupts occur either because of
* a system status change or because a single bit memory error
* occurred. FIXME: At the moment, ignore all this. */
-asmlinkage void
-smp_vic_cmn_interrupt(void)
+fastcall void
+smp_vic_cmn_interrupt(struct pt_regs *regs)
{
static __u8 in_cmn_int = 0;
- static spinlock_t cmn_int_lock = SPIN_LOCK_UNLOCKED;
+ static DEFINE_SPINLOCK(cmn_int_lock);
/* common ints are broadcast, so make sure we only do this once */
_raw_spin_lock(&cmn_int_lock);
/*
* Reschedule call back. Nothing to do, all the work is done
* automatically when we return from the interrupt. */
-asmlinkage void
+static void
smp_reschedule_interrupt(void)
{
/* do nothing */
static struct mm_struct * flush_mm;
static unsigned long flush_va;
-static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_SPINLOCK(tlbstate_lock);
#define FLUSH_ALL 0xffffffff
/*
static inline void
leave_mm (unsigned long cpu)
{
- if (cpu_tlbstate[cpu].state == TLBSTATE_OK)
+ if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
BUG();
- cpu_clear(cpu, cpu_tlbstate[cpu].active_mm->cpu_vm_mask);
+ cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
load_cr3(swapper_pg_dir);
}
/*
* Invalidate call-back
*/
-asmlinkage void
+static void
smp_invalidate_interrupt(void)
{
__u8 cpu = smp_processor_id();
smp_processor_id()));
*/
- if (flush_mm == cpu_tlbstate[cpu].active_mm) {
- if (cpu_tlbstate[cpu].state == TLBSTATE_OK) {
+ if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
+ if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
if (flush_va == FLUSH_ALL)
local_flush_tlb();
else
if (!cpumask)
BUG();
- if ((cpumask & cpus_coerce(cpu_online_map)) != cpumask)
+ if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
BUG();
if (cpumask & (1 << smp_processor_id()))
BUG();
preempt_disable();
- cpu_mask = cpus_coerce(mm->cpu_vm_mask) & ~(1 << smp_processor_id());
+ cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
local_flush_tlb();
if (cpu_mask)
flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
preempt_disable();
- cpu_mask = cpus_coerce(mm->cpu_vm_mask) & ~(1 << smp_processor_id());
+ cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
if (current->active_mm == mm) {
if (current->mm)
preempt_disable();
- cpu_mask = cpus_coerce(mm->cpu_vm_mask) & ~(1 << smp_processor_id());
+ cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
if (current->active_mm == mm) {
if(current->mm)
__flush_tlb_one(va);
}
/* enable the requested IRQs */
-asmlinkage void
+static void
smp_enable_irq_interrupt(void)
{
__u8 irq;
__asm__("hlt");
}
-static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_SPINLOCK(call_lock);
struct call_data_struct {
void (*func) (void *info);
* previously set up. This is used to schedule a function for
* execution on all CPU's - set up the function then broadcast a
* function_interrupt CPI to come here on each CPU */
-asmlinkage void
+static void
smp_call_function_interrupt(void)
{
void (*func) (void *info) = call_data->func;
int wait)
{
struct call_data_struct data;
- __u32 mask = cpus_coerce(cpu_online_map);
+ __u32 mask = cpus_addr(cpu_online_map)[0];
mask &= ~(1<<smp_processor_id());
* no local APIC, so I can't do this
*
* This function is currently a placeholder and is unused in the code */
-asmlinkage void
-smp_apic_timer_interrupt(struct pt_regs regs)
+fastcall void
+smp_apic_timer_interrupt(struct pt_regs *regs)
{
- wrapper_smp_local_timer_interrupt(®s);
+ wrapper_smp_local_timer_interrupt(regs);
}
/* All of the QUAD interrupt GATES */
-asmlinkage void
-smp_qic_timer_interrupt(struct pt_regs regs)
+fastcall void
+smp_qic_timer_interrupt(struct pt_regs *regs)
{
ack_QIC_CPI(QIC_TIMER_CPI);
- wrapper_smp_local_timer_interrupt(®s);
+ wrapper_smp_local_timer_interrupt(regs);
}
-asmlinkage void
-smp_qic_invalidate_interrupt(void)
+fastcall void
+smp_qic_invalidate_interrupt(struct pt_regs *regs)
{
ack_QIC_CPI(QIC_INVALIDATE_CPI);
smp_invalidate_interrupt();
}
-asmlinkage void
-smp_qic_reschedule_interrupt(void)
+fastcall void
+smp_qic_reschedule_interrupt(struct pt_regs *regs)
{
ack_QIC_CPI(QIC_RESCHEDULE_CPI);
smp_reschedule_interrupt();
}
-asmlinkage void
-smp_qic_enable_irq_interrupt(void)
+fastcall void
+smp_qic_enable_irq_interrupt(struct pt_regs *regs)
{
ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
smp_enable_irq_interrupt();
}
-asmlinkage void
-smp_qic_call_function_interrupt(void)
+fastcall void
+smp_qic_call_function_interrupt(struct pt_regs *regs)
{
ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
smp_call_function_interrupt();
}
-asmlinkage void
-smp_vic_cpi_interrupt(struct pt_regs regs)
+fastcall void
+smp_vic_cpi_interrupt(struct pt_regs *regs)
{
__u8 cpu = smp_processor_id();
ack_VIC_CPI(VIC_CPI_LEVEL0);
if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
- wrapper_smp_local_timer_interrupt(®s);
+ wrapper_smp_local_timer_interrupt(regs);
if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
smp_invalidate_interrupt();
if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
unsigned long cpu = smp_processor_id();
__flush_tlb_all();
- if (cpu_tlbstate[cpu].state == TLBSTATE_LAZY)
+ if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
leave_mm(cpu);
}
int cpu = smp_processor_id();
long weight;
- x86_do_profile(regs);
-
+ profile_tick(CPU_PROFILING, regs);
if (--per_cpu(prof_counter, cpu) <= 0) {
/*
* The multiplier may have changed since the last time we got
unsigned long irq_mask = 1 << irq;
int cpu;
- real_mask = cpus_coerce(mask) & voyager_extended_vic_processors;
+ real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
- if(cpus_coerce(mask) == 0)
+ if(cpus_addr(mask)[0] == 0)
/* can't have no cpu's to accept the interrupt -- extremely
* bad things will happen */
return;
git://git.onelab.eu / linux-2.6.git / blobdiff