This commit was manufactured by cvs2svn to create tag

[linux-2.6.git] / arch / i386 / pci / fixup.c

diff --git a/arch/i386/pci/fixup.c b/arch/i386/pci/fixup.c
index 6fc4852..8e2b2d4 100644 (file)
--- a/arch/i386/pci/fixup.c
+++ b/arch/i386/pci/fixup.c
@@ -227,7 +227,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_
  */
 static void __init pci_fixup_nforce2(struct pci_dev *dev)
 {
-       u32 val;
+       u32 val, fixed_val;
+       u8 rev;
+
+       pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
 
        /*
         * Chip  Old value   New value
@@ -237,14 +240,17 @@ static void __init pci_fixup_nforce2(struct pci_dev *dev)
         * Northbridge chip version may be determined by
         * reading the PCI revision ID (0xC1 or greater is C18D).
         */
+       fixed_val = rev < 0xC1 ? 0x1F01FF01 : 0x9F01FF01;
+
        pci_read_config_dword(dev, 0x6c, &val);
 
        /*
-        * Apply fixup if needed, but don't touch disconnect state
+        * Apply fixup only if C1 Halt Disconnect is enabled
+        * (bit28) because it is not supported on some boards.
         */
-       if ((val & 0x00FF0000) != 0x00010000) {
+       if ((val & (1 << 28)) && val != fixed_val) {
                printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
-               pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
+               pci_write_config_dword(dev, 0x6c, fixed_val);
        }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
@@ -340,41 +346,3 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,       PCI_DEVICE_ID_INTEL_MCH_PB1,    pcie_r
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_MCH_PC,     pcie_rootport_aspm_quirk );
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_MCH_PC1,    pcie_rootport_aspm_quirk );
 
-/*
- * Fixup to mark boot BIOS video selected by BIOS before it changes
- *
- * From information provided by "Jon Smirl" <jonsmirl@yahoo.com>
- *
- * The standard boot ROM sequence for an x86 machine uses the BIOS
- * to select an initial video card for boot display. This boot video 
- * card will have it's BIOS copied to C0000 in system RAM. 
- * IORESOURCE_ROM_SHADOW is used to associate the boot video
- * card with this copy. On laptops this copy has to be used since
- * the main ROM may be compressed or combined with another image.
- * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
- * is marked here since the boot video device will be the only enabled
- * video device at this point.
- *
- */static void __devinit pci_fixup_video(struct pci_dev *pdev)
-{
-       struct pci_dev *bridge;
-       struct pci_bus *bus;
-       u16 l;
-
-       if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
-               return;
-
-       /* Is VGA routed to us? */
-       bus = pdev->bus;
-       while (bus) {
-               bridge = bus->self;
-               if (bridge) {
-                       pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &l);
-                       if (!(l & PCI_BRIDGE_CTL_VGA))
-                               return;
-               }
-               bus = bus->parent;
-       }
-       pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);