cpuid_t cpu_id;
nasid_t nasid;
- nasid = COMPACT_TO_NASID_NODEID(cnode);
+ nasid = cnodeid_to_nasid(cnode);
cpu_id = nasid_slice_to_cpuid(nasid, cpu->cpu_info.physid);
if(cpu_id != -1){
snprintf(name, 120, "%s/%s/%c", EDGE_LBL_DISABLED, EDGE_LBL_CPU, 'a' + cpu->cpu_info.physid);
cpuid_t cpu_id;
nasid_t nasid;
- nasid = COMPACT_TO_NASID_NODEID(cnode);
+ nasid = cnodeid_to_nasid(cnode);
cpu_id = nasid_slice_to_cpuid(nasid, cpu->cpu_info.physid);
snprintf(name, 120, "%s/%d/%c",
continue;
}
- hub_cnode = NASID_TO_COMPACT_NODEID(hub_nasid);
+ hub_cnode = nasid_to_cnodeid(hub_nasid);
if (hub_cnode == INVALID_CNODEID) {
continue;
*/
if (hub_nasid != nasid) {
NODEPDA(hub_cnode)->xbow_peer = nasid;
- NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->xbow_peer =
+ NODEPDA(nasid_to_cnodeid(nasid))->xbow_peer =
hub_nasid;
}
}
klcpu_t *cpu;
vertex_hdl_t cpu_dir;
- nasid = COMPACT_TO_NASID_NODEID(cnode);
+ nasid = cnodeid_to_nasid(cnode);
brd = find_lboard_any((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
ASSERT(brd);
int rv;
for (cnode = 0; cnode < numnodes; cnode++) {
- nasid = COMPACT_TO_NASID_NODEID(cnode);
+ nasid = cnodeid_to_nasid(cnode);
brd = find_lboard_class_any((lboard_t *)KL_CONFIG_INFO(nasid),
KLTYPE_ROUTER);
port));
continue;
}
- if (NASID_TO_COMPACT_NODEID(router->rou_port[port].port_nasid)
+ if (nasid_to_cnodeid(router->rou_port[port].port_nasid)
== INVALID_CNODEID) {
continue;
}
lboard_t *brd;
for (cnode = 0; cnode < numnodes; cnode++) {
- nasid = COMPACT_TO_NASID_NODEID(cnode);
+ nasid = cnodeid_to_nasid(cnode);
brd = find_lboard_class_any((lboard_t *)KL_CONFIG_INFO(nasid),
KLTYPE_ROUTER);
do {
- nasid = COMPACT_TO_NASID_NODEID(cnode);
+ nasid = cnodeid_to_nasid(cnode);
klhwg_connect_one_router(hwgraph_root, brd,
cnode, nasid);
int port;
for (cnode = 0; cnode < numionodes; cnode++) {
- nasid = COMPACT_TO_NASID_NODEID(cnode);
+ nasid = cnodeid_to_nasid(cnode);
brd = find_lboard_any((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
continue; /* Port not active */
}
- if (NASID_TO_COMPACT_NODEID(hub->hub_port[port].port_nasid) == INVALID_CNODEID)
+ if (nasid_to_cnodeid(hub->hub_port[port].port_nasid) == INVALID_CNODEID)
continue;
/* Generate a hardware graph path for this board. */
/* Use module as module vertex fastinfo */
memset(buffer, 0, 16);
- format_module_id(buffer, modules[cm]->id, MODULE_FORMAT_BRIEF);
+ format_module_id(buffer, sn_modules[cm]->id, MODULE_FORMAT_BRIEF);
sprintf(name, EDGE_LBL_MODULE "/%s", buffer);
rc = hwgraph_path_add(hwgraph_root, name, &module_vhdl);
rc = rc;
HWGRAPH_DEBUG(__FILE__, __FUNCTION__, __LINE__, module_vhdl, NULL, "Created module path.\n");
- hwgraph_fastinfo_set(module_vhdl, (arbitrary_info_t) modules[cm]);
+ hwgraph_fastinfo_set(module_vhdl, (arbitrary_info_t) sn_modules[cm]);
/* Add system controller */
sprintf(name,