const unsigned long *data = record->data;
switch(record->tag) {
- case BI_APOLLO_MODEL:
- apollo_model=*data;
+ case BI_APOLLO_MODEL:
+ apollo_model=*data;
break;
default:
unknown=1;
}
-
+
return unknown;
}
void dn_setup_model(void) {
-
+
printk("Apollo hardware found: ");
printk("[%s]\n", apollo_models[apollo_model - APOLLO_DN3000]);
break;
case APOLLO_DN3000:
case APOLLO_DN3010:
- sio01_physaddr=SAU8_SIO01_PHYSADDR;
- rtc_physaddr=SAU8_RTC_PHYSADDR;
- pica_physaddr=SAU8_PICA;
- picb_physaddr=SAU8_PICB;
+ sio01_physaddr=SAU8_SIO01_PHYSADDR;
+ rtc_physaddr=SAU8_RTC_PHYSADDR;
+ pica_physaddr=SAU8_PICA;
+ picb_physaddr=SAU8_PICB;
cpuctrl_physaddr=SAU8_CPUCTRL;
timer_physaddr=SAU8_TIMER;
break;
case APOLLO_DN4000:
- sio01_physaddr=SAU7_SIO01_PHYSADDR;
- sio23_physaddr=SAU7_SIO23_PHYSADDR;
- rtc_physaddr=SAU7_RTC_PHYSADDR;
- pica_physaddr=SAU7_PICA;
- picb_physaddr=SAU7_PICB;
+ sio01_physaddr=SAU7_SIO01_PHYSADDR;
+ sio23_physaddr=SAU7_SIO23_PHYSADDR;
+ rtc_physaddr=SAU7_RTC_PHYSADDR;
+ pica_physaddr=SAU7_PICA;
+ picb_physaddr=SAU7_PICB;
cpuctrl_physaddr=SAU7_CPUCTRL;
timer_physaddr=SAU7_TIMER;
break;
panic("Apollo model not yet supported");
break;
case APOLLO_DN3500:
- sio01_physaddr=SAU7_SIO01_PHYSADDR;
- sio23_physaddr=SAU7_SIO23_PHYSADDR;
- rtc_physaddr=SAU7_RTC_PHYSADDR;
- pica_physaddr=SAU7_PICA;
- picb_physaddr=SAU7_PICB;
+ sio01_physaddr=SAU7_SIO01_PHYSADDR;
+ sio23_physaddr=SAU7_SIO23_PHYSADDR;
+ rtc_physaddr=SAU7_RTC_PHYSADDR;
+ pica_physaddr=SAU7_PICA;
+ picb_physaddr=SAU7_PICB;
cpuctrl_physaddr=SAU7_CPUCTRL;
timer_physaddr=SAU7_TIMER;
break;
void dn_serial_console_write (struct console *co, const char *str,unsigned int count)
{
while(count--) {
- if (*str == '\n') {
- sio01.rhrb_thrb = (unsigned char)'\r';
- while (!(sio01.srb_csrb & 0x4))
+ if (*str == '\n') {
+ sio01.rhrb_thrb = (unsigned char)'\r';
+ while (!(sio01.srb_csrb & 0x4))
;
- }
+ }
sio01.rhrb_thrb = (unsigned char)*str++;
while (!(sio01.srb_csrb & 0x4))
;
- }
+ }
}
-
+
void dn_serial_print (const char *str)
{
while (*str) {
int i;
- dn_setup_model();
+ dn_setup_model();
mach_sched_init=dn_sched_init; /* */
mach_init_IRQ=dn_init_IRQ;
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_HEARTBEAT
- mach_heartbeat = dn_heartbeat;
+ mach_heartbeat = dn_heartbeat;
#endif
mach_get_model = dn_get_model;
cpuctrl=0xaa00;
/* clear DMA translation table */
- for(i=0;i<0x400;i++)
+ for(i=0;i<0x400;i++)
addr_xlat_map[i]=0;
-}
+}
irqreturn_t dn_timer_int(int irq, void *dev_id, struct pt_regs *fp) {
volatile unsigned char x;
sched_timer_handler(irq,dev_id,fp);
-
+
x=*(volatile unsigned char *)(timer+3);
x=*(volatile unsigned char *)(timer+5);
void dn_sched_init(irqreturn_t (*timer_routine)(int, void *, struct pt_regs *)) {
- /* program timer 1 */
+ /* program timer 1 */
*(volatile unsigned char *)(timer+3)=0x01;
*(volatile unsigned char *)(timer+1)=0x40;
*(volatile unsigned char *)(timer+5)=0x09;
for(;;);
}
-
+
void dn_dummy_waitbut(void) {
dn_serial_print("waitbut\n");
static void dn_heartbeat(int on) {
- if(on) {
+ if(on) {
dn_cpuctrl&=~0x100;
cpuctrl=dn_cpuctrl;
}