*/
#include <linux/types.h>
-#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/hardirq.h>
+#include <asm/compiler.h>
#include <asm/mipsregs.h>
-#include <asm/ptrace.h>
#include <asm/time.h>
#include <asm/div64.h>
#include <asm/mach-au1x00/au1000.h>
#include <linux/mc146818rtc.h>
#include <linux/timex.h>
-extern void startup_match20_interrupt(void);
-extern void do_softirq(void);
-extern volatile unsigned long wall_jiffies;
-unsigned long missed_heart_beats = 0;
-
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
int no_au1xxx_32khz;
-void (*au1k_wait_ptr)(void);
-
-/* Cycle counter value at the previous timer interrupt.. */
-static unsigned int timerhi = 0, timerlo = 0;
+extern int allow_au1k_wait; /* default off for CP0 Counter */
#ifdef CONFIG_PM
-#define MATCH20_INC 328
-extern void startup_match20_interrupt(void);
+#if HZ < 100 || HZ > 1000
+#error "unsupported HZ value! Must be in [100,1000]"
+#endif
+#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
+extern void startup_match20_interrupt(irq_handler_t handler);
static unsigned long last_pc0, last_match20;
#endif
-static spinlock_t time_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_SPINLOCK(time_lock);
static inline void ack_r4ktimer(unsigned long newval)
{
* is provably more robust.
*/
unsigned long wtimer;
-void mips_timer_interrupt(struct pt_regs *regs)
+
+void mips_timer_interrupt(void)
{
int irq = 63;
- unsigned long count;
irq_enter();
kstat_this_cpu.irqs[irq]++;
goto null;
do {
- count = read_c0_count();
- timerhi += (count < timerlo); /* Wrap around */
- timerlo = count;
-
kstat_this_cpu.irqs[irq]++;
- do_timer(regs);
+ do_timer(1);
+#ifndef CONFIG_SMP
+ update_process_times(user_mode(get_irq_regs()));
+#endif
r4k_cur += r4k_offset;
ack_r4ktimer(r4k_cur);
null:
ack_r4ktimer(0);
+ irq_exit();
}
#ifdef CONFIG_PM
-void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
+irqreturn_t counter0_irq(int irq, void *dev_id)
{
unsigned long pc0;
int time_elapsed;
static int jiffie_drift = 0;
- kstat.irqs[0][irq]++;
if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
/* should never happen! */
- printk(KERN_WARNING "counter 0 w status eror\n");
- return;
+ printk(KERN_WARNING "counter 0 w status error\n");
+ return IRQ_NONE;
}
pc0 = au_readl(SYS_TOYREAD);
}
while (time_elapsed > 0) {
- do_timer(regs);
+ do_timer(1);
+#ifndef CONFIG_SMP
+ update_process_times(user_mode(get_irq_regs()));
+#endif
time_elapsed -= MATCH20_INC;
last_match20 += MATCH20_INC;
jiffie_drift++;
if (jiffie_drift >= 999) {
jiffie_drift -= 999;
- do_timer(regs); /* increment jiffies by one */
+ do_timer(1); /* increment jiffies by one */
+#ifndef CONFIG_SMP
+ update_process_times(user_mode(get_irq_regs()));
+#endif
}
+
+ return IRQ_HANDLED;
}
/* When we wakeup from sleep, we have to "catch up" on all of the
*/
unsigned long cal_r4koff(void)
{
- unsigned long count;
unsigned long cpu_speed;
unsigned long flags;
unsigned long counter;
#if defined(CONFIG_AU1000_USE32K)
{
- unsigned long start, end;
+ unsigned long start, end, count;
start = au_readl(SYS_RTCREAD);
start += 2;
cpu_speed = count * 2;
}
#else
- cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
+ cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
AU1000_SRC_CLK;
- count = cpu_speed / 2;
#endif
}
else {
* NOTE: some old silicon doesn't allow reading the PLL.
*/
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
- count = cpu_speed / 2;
no_au1xxx_32khz = 1;
}
- mips_hpt_frequency = count;
+ mips_hpt_frequency = cpu_speed;
// Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
spin_unlock_irqrestore(&time_lock, flags);
return (cpu_speed / HZ);
}
-/* This is for machines which generate the exact clock. */
-#define USECS_PER_JIFFY (1000000/HZ)
-#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
-
-
-static unsigned long
-div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
-{
- unsigned long r0;
- do_div64_32(r0, v1, v2, v3);
- return r0;
-}
-
-static unsigned long do_fast_cp0_gettimeoffset(void)
-{
- u32 count;
- unsigned long res, tmp;
- unsigned long r0;
-
- /* Last jiffy when do_fast_gettimeoffset() was called. */
- static unsigned long last_jiffies=0;
- unsigned long quotient;
-
- /*
- * Cached "1/(clocks per usec)*2^32" value.
- * It has to be recalculated once each jiffy.
- */
- static unsigned long cached_quotient=0;
-
- tmp = jiffies;
-
- quotient = cached_quotient;
-
- if (tmp && last_jiffies != tmp) {
- last_jiffies = tmp;
- if (last_jiffies != 0) {
- r0 = div64_32(timerhi, timerlo, tmp);
- quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
- cached_quotient = quotient;
- }
- }
-
- /* Get last timer tick in absolute kernel time */
- count = read_c0_count();
-
- /* .. relative to previous jiffy (32 bits is enough) */
- count -= timerlo;
-
- __asm__("multu\t%1,%2\n\t"
- "mfhi\t%0"
- :"=r" (res)
- :"r" (count),
- "r" (quotient));
-
- /*
- * Due to possible jiffies inconsistencies, we need to check
- * the result so that we'll get a timer that is monotonic.
- */
- if (res >= USECS_PER_JIFFY)
- res = USECS_PER_JIFFY-1;
-
- return res;
-}
-
-#ifdef CONFIG_PM
-static unsigned long do_fast_pm_gettimeoffset(void)
-{
- unsigned long pc0;
- unsigned long offset;
-
- pc0 = au_readl(SYS_TOYREAD);
- au_sync();
- offset = pc0 - last_pc0;
- if (offset > 2*MATCH20_INC) {
- printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
- (unsigned)offset, (unsigned)last_pc0,
- (unsigned)last_match20, (unsigned)pc0);
- }
- offset = (unsigned long)((offset * 305) / 10);
- return offset;
-}
-#endif
-
-void au1xxx_timer_setup(struct irqaction *irq)
+void __init plat_timer_setup(struct irqaction *irq)
{
- unsigned int est_freq;
- extern unsigned long (*do_gettimeoffset)(void);
- extern void au1k_wait(void);
+ unsigned int est_freq;
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
- //est_freq = 2*r4k_offset*HZ;
- est_freq = r4k_offset*HZ;
+ //est_freq = 2*r4k_offset*HZ;
+ est_freq = r4k_offset*HZ;
est_freq += 5000; /* round */
est_freq -= est_freq%10000;
- printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
+ printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
set_au1x00_speed(est_freq);
set_au1x00_lcd_clock(); // program the LCD clock
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
- /* no RTC on the pb1000 */
- xtime.tv_sec = 0;
- //xtime.tv_usec = 0;
-
#ifdef CONFIG_PM
/*
* setup counter 0, since it keeps ticking after a
unsigned int c0_status;
printk("WARNING: no 32KHz clock found.\n");
- do_gettimeoffset = do_fast_cp0_gettimeoffset;
/* Ensure we get CPO_COUNTER interrupts.
*/
au_sync();
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
- /* setup match20 to interrupt once every 10ms */
+ /* setup match20 to interrupt once every HZ */
last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
- startup_match20_interrupt();
-
- do_gettimeoffset = do_fast_pm_gettimeoffset;
+ startup_match20_interrupt(counter0_irq);
/* We can use the real 'wait' instruction.
*/
- au1k_wait_ptr = au1k_wait;
+ allow_au1k_wait = 1;
}
-#else
- /* We have to do this here instead of in timer_init because
- * the generic code in arch/mips/kernel/time.c will write
- * over our function pointer.
- */
- do_gettimeoffset = do_fast_cp0_gettimeoffset;
#endif
}