tmp = regs->lo;
break;
case FPC_CSR:
- if (cpu_has_fpu)
- tmp = child->thread.fpu.hard.fcr31;
- else
- tmp = child->thread.fpu.soft.fcr31;
+ tmp = child->thread.fpu.fcr31;
break;
case FPC_EIR: { /* implementation / version register */
unsigned int flags;
unsigned int mtflags;
#endif /* CONFIG_MIPS_MT_SMTC */
+ preempt_disable();
if (!cpu_has_fpu) {
+ preempt_enable();
tmp = 0;
break;
}
mtflags = dmt();
#endif /* CONFIG_MIPS_MT_SMTC */
- preempt_disable();
if (cpu_has_mipsmt) {
unsigned int vpflags = dvpe();
flags = read_c0_status();
if (!tsk_used_math(child)) {
/* FP not yet used */
- memset(&child->thread.fpu.hard, ~0,
- sizeof(child->thread.fpu.hard));
- child->thread.fpu.hard.fcr31 = 0;
+ memset(&child->thread.fpu, ~0,
+ sizeof(child->thread.fpu));
+ child->thread.fpu.fcr31 = 0;
}
/*
* The odd registers are actually the high order bits
regs->lo = data;
break;
case FPC_CSR:
- if (cpu_has_fpu)
- child->thread.fpu.hard.fcr31 = data;
- else
- child->thread.fpu.soft.fcr31 = data;
+ child->thread.fpu.fcr31 = data;
break;
case DSP_BASE ... DSP_BASE + 5: {
dspreg_t *dregs;