fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / mips / kernel / unaligned.c

diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 4516e35..7e7d548 100644 (file)
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -72,7 +72,6 @@
  *       A store crossing a page boundary might be executed only partially.
  *       Undo the partial store in this case.
  */
-#include <linux/config.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/signal.h>
@@ -94,7 +93,7 @@ unsigned long unaligned_instructions;
 #endif
 
 static inline int emulate_load_store_insn(struct pt_regs *regs,
-       void *addr, unsigned long pc,
+       void __user *addr, unsigned int __user *pc,
        unsigned long **regptr, unsigned long *newvalue)
 {
        union mips_instruction insn;
@@ -107,7 +106,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
        /*
         * This load never faults.
         */
-       __get_user(insn.word, (unsigned int *)pc);
+       __get_user(insn.word, pc);
 
        switch (insn.i_format.opcode) {
        /*
@@ -143,7 +142,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
         * The remaining opcodes are the ones that are really of interest.
         */
        case lh_op:
-               if (verify_area(VERIFY_READ, addr, 2))
+               if (!access_ok(VERIFY_READ, addr, 2))
                        goto sigbus;
 
                __asm__ __volatile__ (".set\tnoat\n"
@@ -176,7 +175,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                break;
 
        case lw_op:
-               if (verify_area(VERIFY_READ, addr, 4))
+               if (!access_ok(VERIFY_READ, addr, 4))
                        goto sigbus;
 
                __asm__ __volatile__ (
@@ -206,7 +205,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                break;
 
        case lhu_op:
-               if (verify_area(VERIFY_READ, addr, 2))
+               if (!access_ok(VERIFY_READ, addr, 2))
                        goto sigbus;
 
                __asm__ __volatile__ (
@@ -240,7 +239,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                break;
 
        case lwu_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                /*
                 * A 32-bit kernel might be running on a 64-bit processor.  But
                 * if we're on a 32-bit processor and an i-cache incoherency
@@ -248,7 +247,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 * would blow up, so for now we don't handle unaligned 64-bit
                 * instructions on 32-bit kernels.
                 */
-               if (verify_area(VERIFY_READ, addr, 4))
+               if (!access_ok(VERIFY_READ, addr, 4))
                        goto sigbus;
 
                __asm__ __volatile__ (
@@ -278,13 +277,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                *newvalue = value;
                *regptr = &regs->regs[insn.i_format.rt];
                break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
                /* Cannot handle 64-bit instructions in 32-bit kernel */
                goto sigill;
 
        case ld_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                /*
                 * A 32-bit kernel might be running on a 64-bit processor.  But
                 * if we're on a 32-bit processor and an i-cache incoherency
@@ -292,7 +291,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 * would blow up, so for now we don't handle unaligned 64-bit
                 * instructions on 32-bit kernels.
                 */
-               if (verify_area(VERIFY_READ, addr, 8))
+               if (!access_ok(VERIFY_READ, addr, 8))
                        goto sigbus;
 
                __asm__ __volatile__ (
@@ -320,13 +319,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                *newvalue = value;
                *regptr = &regs->regs[insn.i_format.rt];
                break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
                /* Cannot handle 64-bit instructions in 32-bit kernel */
                goto sigill;
 
        case sh_op:
-               if (verify_area(VERIFY_WRITE, addr, 2))
+               if (!access_ok(VERIFY_WRITE, addr, 2))
                        goto sigbus;
 
                value = regs->regs[insn.i_format.rt];
@@ -362,7 +361,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                break;
 
        case sw_op:
-               if (verify_area(VERIFY_WRITE, addr, 4))
+               if (!access_ok(VERIFY_WRITE, addr, 4))
                        goto sigbus;
 
                value = regs->regs[insn.i_format.rt];
@@ -392,7 +391,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                break;
 
        case sd_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                /*
                 * A 32-bit kernel might be running on a 64-bit processor.  But
                 * if we're on a 32-bit processor and an i-cache incoherency
@@ -400,7 +399,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 * would blow up, so for now we don't handle unaligned 64-bit
                 * instructions on 32-bit kernels.
                 */
-               if (verify_area(VERIFY_WRITE, addr, 8))
+               if (!access_ok(VERIFY_WRITE, addr, 8))
                        goto sigbus;
 
                value = regs->regs[insn.i_format.rt];
@@ -428,7 +427,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                if (res)
                        goto fault;
                break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
                /* Cannot handle 64-bit instructions in 32-bit kernel */
                goto sigill;
@@ -494,8 +493,8 @@ asmlinkage void do_ade(struct pt_regs *regs)
 {
        unsigned long *regptr, newval;
        extern int do_dsemulret(struct pt_regs *);
+       unsigned int __user *pc;
        mm_segment_t seg;
-       unsigned long pc;
 
        /*
         * Address errors may be deliberately induced by the FPU emulator to
@@ -515,7 +514,7 @@ asmlinkage void do_ade(struct pt_regs *regs)
        if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1))
                goto sigbus;
 
-       pc = exception_epc(regs);
+       pc = (unsigned int __user *) exception_epc(regs);
        if ((current->thread.mflags & MF_FIXADE) == 0)
                goto sigbus;
 
@@ -526,7 +525,7 @@ asmlinkage void do_ade(struct pt_regs *regs)
        seg = get_fs();
        if (!user_mode(regs))
                set_fs(KERNEL_DS);
-       if (!emulate_load_store_insn(regs, (void *)regs->cp0_badvaddr, pc,
+       if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc,
                                     &regptr, &newval)) {
                compute_return_epc(regs);
                /*