#include <asm/war.h>
#include <asm/cacheflush.h> /* for run_uncached() */
-
-/*
- * Special Variant of smp_call_function for use by cache functions:
- *
- * o No return value
- * o collapses to normal function call on UP kernels
- * o collapses to normal function call on systems with a single shared
- * primary cache.
- */
-static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
- int retry, int wait)
-{
- preempt_disable();
-
-#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
- smp_call_function(func, info, retry, wait);
-#endif
- func(info);
- preempt_enable();
-}
-
/*
* Must die.
*/
if (!cpu_has_dc_aliases)
return;
- r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
+ on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
}
static inline void local_r4k___flush_cache_all(void * args)
case CPU_R4400MC:
case CPU_R10000:
case CPU_R12000:
- case CPU_R14000:
r4k_blast_scache();
}
}
static void r4k___flush_cache_all(void)
{
- r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
+ on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
}
static inline void local_r4k_flush_cache_range(void * args)
static void r4k_flush_cache_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
- r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
+ on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
}
static inline void local_r4k_flush_cache_mm(void * args)
if (!cpu_has_dc_aliases)
return;
- r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
+ on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
}
struct flush_cache_page_args {
args.addr = addr;
args.pfn = pfn;
- r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
+ on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
}
static inline void local_r4k_flush_data_cache_page(void * addr)
static void r4k_flush_data_cache_page(unsigned long addr)
{
- r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
+ on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
}
struct flush_icache_range_args {
args.start = start;
args.end = end;
- r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+ on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
instruction_hazard();
}
args.vma = vma;
args.page = page;
- r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
+ on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
}
static void r4k_flush_cache_sigtramp(unsigned long addr)
{
- r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
+ on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
}
static void r4k_flush_icache_all(void)
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
c->icache.ways = 2;
- c->icache.waybit = __ffs(icache_size/2);
+ c->icache.waybit = ffs(icache_size/2) - 1;
dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
c->dcache.ways = 2;
- c->dcache.waybit= __ffs(dcache_size/2);
+ c->dcache.waybit= ffs(dcache_size/2) - 1;
c->options |= MIPS_CPU_CACHE_CDEX_P;
break;
c->dcache.waybit = 0;
c->options |= MIPS_CPU_CACHE_CDEX_P;
- c->options |= MIPS_CPU_PREFETCH;
break;
case CPU_R4000PC:
case CPU_R10000:
case CPU_R12000:
- case CPU_R14000:
icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
c->icache.linesz = 64;
c->icache.ways = 2;
icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
c->icache.ways = 2;
- c->icache.waybit = __ffs(icache_size/2);
+ c->icache.waybit = ffs(icache_size/2) - 1;
dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
c->dcache.ways = 2;
- c->dcache.waybit = __ffs(dcache_size/2);
+ c->dcache.waybit = ffs(dcache_size/2) - 1;
c->options |= MIPS_CPU_CACHE_CDEX_P;
break;
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
c->icache.ways = 4;
- c->icache.waybit = __ffs(icache_size / c->icache.ways);
+ c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
c->dcache.ways = 4;
- c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
+ c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
c->options |= MIPS_CPU_CACHE_CDEX_P;
icache_size = c->icache.sets *
c->icache.ways *
c->icache.linesz;
- c->icache.waybit = __ffs(icache_size/c->icache.ways);
+ c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
if (config & 0x8) /* VI bit */
c->icache.flags |= MIPS_CACHE_VTAG;
dcache_size = c->dcache.sets *
c->dcache.ways *
c->dcache.linesz;
- c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
+ c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
c->options |= MIPS_CPU_PREFETCH;
break;
c->dcache.flags |= MIPS_CACHE_PINDEX;
case CPU_R10000:
case CPU_R12000:
- case CPU_R14000:
case CPU_SB1:
break;
case CPU_24K:
- case CPU_34K:
if (!(read_c0_config7() & (1 << 16)))
default:
if (c->dcache.waysize > PAGE_SIZE)
case CPU_R10000:
case CPU_R12000:
- case CPU_R14000:
scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
c->scache.linesz = 64 << ((config >> 13) & 1);
c->scache.ways = 2;
c->options |= MIPS_CPU_SUBSET_CACHES;
}
-void au1x00_fixup_config_od(void)
-{
- /*
- * c0_config.od (bit 19) was write only (and read as 0)
- * on the early revisions of Alchemy SOCs. It disables the bus
- * transaction overlapping and needs to be set to fix various errata.
- */
- switch (read_c0_prid()) {
- case 0x00030100: /* Au1000 DA */
- case 0x00030201: /* Au1000 HA */
- case 0x00030202: /* Au1000 HB */
- case 0x01030200: /* Au1500 AB */
- /*
- * Au1100 errata actually keeps silence about this bit, so we set it
- * just in case for those revisions that require it to be set according
- * to arch/mips/au1000/common/cputable.c
- */
- case 0x02030200: /* Au1100 AB */
- case 0x02030201: /* Au1100 BA */
- case 0x02030202: /* Au1100 BC */
- set_c0_config(1 << 19);
- break;
- }
-}
-
static inline void coherency_setup(void)
{
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
case CPU_R4400MC:
clear_c0_config(CONF_CU);
break;
- /*
- * We need to catch the ealry Alchemy SOCs with
- * the write-only co_config.od bit and set it back to one...
- */
- case CPU_AU1000: /* rev. DA, HA, HB */
- case CPU_AU1100: /* rev. AB, BA, BC ?? */
- case CPU_AU1500: /* rev. AB */
- au1x00_fixup_config_od();
- break;
}
}
flush_cache_sigtramp = r4k_flush_cache_sigtramp;
flush_icache_all = r4k_flush_icache_all;
- local_flush_data_cache_page = local_r4k_flush_data_cache_page;
flush_data_cache_page = r4k_flush_data_cache_page;
flush_icache_range = r4k_flush_icache_range;
git://git.onelab.eu / linux-2.6.git / blobdiff