emit_instruction(mi);
}
-static void __init __build_store_reg(int reg)
+static void __build_store_reg(int reg)
{
union mips_instruction mi;
unsigned int width;
case CPU_R10000:
case CPU_R12000:
pref_src_mode = Pref_LoadStreamed;
- pref_dst_mode = Pref_StoreStreamed;
+ pref_dst_mode = Pref_StoreRetained;
break;
default: