* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com)
*/
-#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
-extern void except_vec0_generic(void);
-extern void except_vec0_r4000(void);
-extern void except_vec1_generic(void);
-extern void except_vec1_r10k(void);
+extern void build_tlb_refill_handler(void);
#define NTLB_ENTRIES 64
#define NTLB_ENTRIES_HALF 32
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
- write_c0_entryhi(KSEG0);
+ write_c0_entryhi(CKSEG0);
if(idx < 0)
continue;
tlb_write_indexed();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
- write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1)));
+ write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT+1)));
if (idx < 0)
continue;
tlb_write_indexed();
idx = read_c0_index();
write_c0_entrylo0(0);
write_c0_entrylo1(0);
- write_c0_entryhi(KSEG0);
+ write_c0_entryhi(CKSEG0);
if (idx < 0)
goto finish;
tlb_write_indexed();
write_c0_entrylo1(0);
if (idx >= 0) {
/* Make sure all entries differ. */
- write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1)));
+ write_c0_entryhi(CKSEG0+(idx<<(PAGE_SHIFT+1)));
tlb_write_indexed();
}
write_c0_entryhi(oldpid);
{
unsigned long flags;
pgd_t *pgdp;
+ pud_t *pudp;
pmd_t *pmdp;
pte_t *ptep;
int idx, pid;
write_c0_entryhi(address | (pid));
pgdp = pgd_offset(vma->vm_mm, address);
tlb_probe();
- pmdp = pmd_offset(pgdp, address);
+ pudp = pud_offset(pgdp, address);
+ pmdp = pmd_offset(pudp, address);
idx = read_c0_index();
ptep = pte_offset_map(pmdp, address);
write_c0_entrylo0(pte_val(*ptep++) >> 6);
/* Did I tell you that ARC SUCKS? */
-#ifdef CONFIG_MIPS32
- memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
- memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80);
- flush_icache_range(KSEG0, KSEG0 + 0x100);
-#endif
-#ifdef CONFIG_MIPS64
- memcpy((void *)(CKSEG0 + 0x000), &except_vec0_generic, 0x80);
- memcpy((void *)(CKSEG0 + 0x080), except_vec1_r10k, 0x80);
- flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100);
-#endif
+ build_tlb_refill_handler();
}