* BRIEF MODULE DESCRIPTION
* Momentum Computer Jaguar-ATX board dependent boot routines
*
- * Copyright (C) 1996, 1997, 2001 Ralf Baechle
+ * Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2000 RidgeRun, Inc.
* Copyright (C) 2001 Red Hat, Inc.
* Copyright (C) 2002 Momentum Computer
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#include <linux/config.h>
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
+#include <linux/module.h>
+#include <linux/pci.h>
#include <linux/swap.h>
#include <linux/ioport.h>
+#include <linux/pm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
+#include <linux/mv643xx.h>
+
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/pci.h>
-#include <asm/pci_channel.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/reboot.h>
#include <asm/tlbflush.h>
-#include <asm/mv64340.h>
#include "jaguar_atx_fpga.h"
static __init void wire_stupidity_into_tlb(void)
{
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
write_c0_wired(0);
local_flush_tlb_all();
// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
// 0xfe000000UL, PM_16M);
- mv64340_base = 0xf4000000;
+ marvell_base = 0xf4000000;
//mv64340_sram_base = 0xfe000000; /* Currently unused */
#endif
}
-unsigned long mv64340_base = 0xf4000000L;
+unsigned long marvell_base = 0xf4000000L;
unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
unsigned long uart_base = 0xfd000000L;
static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
+EXPORT_SYMBOL(marvell_base);
+
static __init int per_cpu_mappings(void)
{
- mv64340_base = (unsigned long) ioremap(0xf4000000, 0x10000);
+ marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
rtc_base = ioremap(0xfc000000UL, 0x8000);
unsigned long m48t37y_get_time(void)
{
unsigned int year, month, day, hour, min, sec;
+ unsigned long flags;
+ spin_lock_irqsave(&rtc_lock, flags);
/* stop the update */
rtc_base[0x7ff8] = 0x40;
/* start the update */
rtc_base[0x7ff8] = 0x00;
+ spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
int m48t37y_set_time(unsigned long sec)
{
struct rtc_time tm;
+ unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
+ spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
rtc_base[0x7ff8] = 0x80;
/* disable writing */
rtc_base[0x7ff8] = 0x00;
+ spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
-void momenco_timer_setup(struct irqaction *irq)
+void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(8, irq);
}
wire_stupidity_into_tlb();
mips_hpt_frequency = cpu_clock / 2;
- board_timer_setup = momenco_timer_setup;
- rtc_get_time = m48t37y_get_time;
- rtc_set_time = m48t37y_set_time;
+ rtc_mips_get_time = m48t37y_get_time;
+ rtc_mips_set_time = m48t37y_set_time;
}
static struct resource mv_pci_io_mem0_resource = {
.flags = IORESOURCE_MEM
};
-extern struct pci_ops mv64340_bus0_pci_ops;
-
-static struct pci_controller mv_bus0_controller = {
- .pci_ops = &mv64340_bus0_pci_ops,
- .mem_resource = &mv_pci_mem0_resource,
- .io_resource = &mv_pci_io_mem0_resource,
+static struct mv_pci_controller mv_bus0_controller = {
+ .pcic = {
+ .pci_ops = &mv_pci_ops,
+ .mem_resource = &mv_pci_mem0_resource,
+ .io_resource = &mv_pci_io_mem0_resource,
+ },
+ .config_addr = MV64340_PCI_0_CONFIG_ADDR,
+ .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
};
static uint32_t mv_io_base, mv_io_size;
mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
- mv_pci_io_mem0_resource.start = 0;
- mv_pci_io_mem0_resource.end = io_size - 1;
- mv_pci_mem0_resource.start = mem0_base;
- mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
- mv_bus0_controller.mem_offset = mem0_base;
- mv_bus0_controller.io_offset = 0;
+ mv_pci_io_mem0_resource.start = 0;
+ mv_pci_io_mem0_resource.end = io_size - 1;
+ mv_pci_mem0_resource.start = mem0_base;
+ mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
+ mv_bus0_controller.pcic.mem_offset = mem0_base;
+ mv_bus0_controller.pcic.io_offset = 0;
ioport_resource.end = io_size - 1;
- register_pci_controller(&mv_bus0_controller);
+ register_pci_controller(&mv_bus0_controller.pcic);
mv_io_base = io_base;
mv_io_size = io_size;
.flags = IORESOURCE_MEM
};
-extern struct pci_ops mv64340_bus1_pci_ops;
-
-static struct pci_controller mv_bus1_controller = {
- .pci_ops = &mv64340_bus1_pci_ops,
- .mem_resource = &mv_pci_mem1_resource,
- .io_resource = &mv_pci_io_mem1_resource,
+static struct mv_pci_controller mv_bus1_controller = {
+ .pcic = {
+ .pci_ops = &mv_pci_ops,
+ .mem_resource = &mv_pci_mem1_resource,
+ .io_resource = &mv_pci_io_mem1_resource,
+ },
+ .config_addr = MV64340_PCI_1_CONFIG_ADDR,
+ .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
};
static __init void ja_pci1_init(void)
* the first. A gap is no problem but would waste address space for
* remapping the port space.
*/
- mv_pci_io_mem1_resource.start = mv_io_size;
- mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
- mv_pci_mem1_resource.start = mem0_base;
- mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
- mv_bus1_controller.mem_offset = mem0_base;
- mv_bus1_controller.io_offset = 0;
+ mv_pci_io_mem1_resource.start = mv_io_size;
+ mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
+ mv_pci_mem1_resource.start = mem0_base;
+ mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
+ mv_bus1_controller.pcic.mem_offset = mem0_base;
+ mv_bus1_controller.pcic.io_offset = 0;
ioport_resource.end = io_base + io_size -mv_io_base - 1;
- register_pci_controller(&mv_bus1_controller);
+ register_pci_controller(&mv_bus1_controller.pcic);
mv_io_size = io_base + io_size - mv_io_base;
}
arch_initcall(ja_pci_init);
-static int __init momenco_jaguar_atx_setup(void)
+void __init plat_mem_setup(void)
{
unsigned int tmpword;
_machine_restart = momenco_jaguar_restart;
_machine_halt = momenco_jaguar_halt;
- _machine_power_off = momenco_jaguar_power_off;
+ pm_power_off = momenco_jaguar_power_off;
/*
- * initrd_start = (ulong)jaguar_initrd_start;
- * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
+ * initrd_start = (unsigned long)jaguar_initrd_start;
+ * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size;
* initrd_below_start_ok = 1;
*/
* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2),
- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
/* Turn off the Bit-Error LED */
JAGUAR_FPGA_WRITE(0x80, CLR);
#ifdef GEMDEBUG_TRACEBUFFER
{
unsigned int tbControl;
- tbControl =
+ tbControl =
0 << 26 | /* post trigger delay 0 */
- 0x2 << 16 | /* sequential trace mode */
+ 0x2 << 16 | /* sequential trace mode */
// 0x0 << 16 | /* non-sequential trace mode */
// 0xf << 4 | /* watchpoints disabled */
2 << 2 | /* armed */
}
#endif
-
- return 0;
}
-
-early_initcall(momenco_jaguar_atx_setup);
git://git.onelab.eu / linux-2.6.git / blobdiff