#include <linux/slab.h>
#include <linux/random.h>
#include <linux/bitops.h>
+#include <linux/mv643xx.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
-#include <asm/mv64340.h>
#include <asm/system.h>
-extern asmlinkage void ocelot_handle_int(void);
extern void uart_irq_init(void);
extern void cpci_irq_init(void);
static struct irqaction cascade_fpga = {
- no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
+ no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
};
static struct irqaction cascade_mv64340 = {
- no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
+ no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
};
+extern void ll_uart_irq(void);
+extern void ll_cpci_irq(void);
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned int pending = read_c0_cause() & read_c0_status();
+
+ if (pending & STATUSF_IP0)
+ do_IRQ(0);
+ else if (pending & STATUSF_IP1)
+ do_IRQ(1);
+ else if (pending & STATUSF_IP2)
+ do_IRQ(2);
+ else if (pending & STATUSF_IP3)
+ ll_uart_irq();
+ else if (pending & STATUSF_IP4)
+ do_IRQ(4);
+ else if (pending & STATUSF_IP5)
+ ll_cpci_irq();
+ else if (pending & STATUSF_IP6)
+ ll_mv64340_irq();
+ else if (pending & STATUSF_IP7)
+ do_IRQ(7);
+ else
+ spurious_interrupt();
+}
+
void __init arch_init_irq(void)
{
/*
*/
clear_c0_status(ST0_IM);
- /* Sets the first-level interrupt dispatcher. */
- set_except_vector(0, ocelot_handle_int);
mips_cpu_irq_init(0);
/* set up the cascading interrupts */