* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
-#include <linux/config.h>
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
+#include <linux/pm.h>
#include <linux/timex.h>
#include <linux/vmalloc.h>
+#include <linux/mv643xx.h>
+
#include <asm/time.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/processor.h>
-#include <asm/ptrace.h>
#include <asm/reboot.h>
+#include <asm/marvell.h>
#include <linux/bootmem.h>
#include <linux/blkdev.h>
-#include <asm/mv64340.h>
#include "ocelot_c_fpga.h"
-unsigned long mv64340_base;
-extern unsigned long mv64340_sram_base;
-unsigned long cpu_clock;
+unsigned long marvell_base;
+unsigned int cpu_clock;
/* These functions are used for rebooting or halting the machine*/
extern void momenco_ocelot_restart(char *command);
*/
printk("PMON_v2_setup\n");
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
/* fpga, rtc, and uart */
/* m-sys and internal SRAM */
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
- mv64340_base = 0xfffffffff4000000;
- mv64340_sram_base = 0xfffffffffe000000;
+ marvell_base = 0xfffffffff4000000;
#else
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
/* m-sys and internal SRAM */
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
- mv64340_base = 0xf4000000;
- mv64340_sram_base = 0xfe000000;
+ marvell_base = 0xf4000000;
#endif
}
unsigned long m48t37y_get_time(void)
{
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
#else
unsigned char* rtc_base = (unsigned char*)0xfc800000;
#endif
unsigned int year, month, day, hour, min, sec;
+ unsigned long flags;
+ spin_lock_irqsave(&rtc_lock, flags);
/* stop the update */
rtc_base[0x7ff8] = 0x40;
/* start the update */
rtc_base[0x7ff8] = 0x00;
+ spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
int m48t37y_set_time(unsigned long sec)
{
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
#else
unsigned char* rtc_base = (unsigned char*)0xfc800000;
#endif
struct rtc_time tm;
+ unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
+ spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
rtc_base[0x7ff8] = 0x80;
rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
/* day of week -- not really used, but let's keep it up-to-date */
- rtc_base[0x7ffc] = CONV_BIN2BCD(tm.tm_wday + 1);
+ rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
/* disable writing */
rtc_base[0x7ff8] = 0x00;
+ spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
-void momenco_timer_setup(struct irqaction *irq)
+void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(7, irq);
}
#error Unknown CPU for this board
#endif
printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
- board_timer_setup = momenco_timer_setup;
- rtc_get_time = m48t37y_get_time;
- rtc_set_time = m48t37y_set_time;
+ rtc_mips_get_time = m48t37y_get_time;
+ rtc_mips_set_time = m48t37y_set_time;
}
-static void __init momenco_ocelot_c_setup(void)
+void __init plat_mem_setup(void)
{
unsigned int tmpword;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
- _machine_power_off = momenco_ocelot_power_off;
+ pm_power_off = momenco_ocelot_power_off;
/*
- * initrd_start = (ulong)ocelot_initrd_start;
- * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
+ * initrd_start = (unsigned long)ocelot_initrd_start;
+ * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
* initrd_below_start_ok = 1;
*/
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
- MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
- MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
+ MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
do {}
- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
- while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
+ while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
do {}
- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
- while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
- MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
- MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
+ while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
+ MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
+ MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE(0x80, CLR);
}
}
-early_initcall(momenco_ocelot_c_setup);
-
-#ifndef CONFIG_MIPS64
-/* This needs to be one of the first initcalls, because no I/O port access
- can work before this */
+/*
+ * This needs to be one of the first initcalls, because no I/O port access
+ * can work before this
+ */
static int io_base_ioremap(void)
{
- /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
- void *io_remap_range = ioremap(0xc0000000, 0x30000000);
+ void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
- if (!io_remap_range) {
+ if (!io_remap_range)
panic("Could not ioremap I/O port range");
- }
- printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
- set_io_port_base(io_remap_range - 0xc0000000);
+
+ set_io_port_base((unsigned long) io_remap_range);
return 0;
}
module_init(io_base_ioremap);
-#endif
git://git.onelab.eu / linux-2.6.git / blobdiff