#include <asm/pmon.h>
#include <asm/titan_dep.h>
+#include <asm/time.h>
#define LAUNCHSTACK_SIZE 256
-static spinlock_t launch_lock __initdata;
+static __initdata DEFINE_SPINLOCK(launch_lock);
static unsigned long secondary_sp __initdata;
static unsigned long secondary_gp __initdata;
{
spin_lock(&launch_lock);
- debug_vectors->cpustart(1, &prom_smp_bootstrap,
- launchstack + LAUNCHSTACK_SIZE, 0);
+ pmon_cpustart(1, &prom_smp_bootstrap,
+ launchstack + LAUNCHSTACK_SIZE, 0);
}
/*
* We don't want to start the secondary CPU yet nor do we have a nice probing
* feature in PMON so we just assume presence of the secondary core.
*/
-void prom_prepare_cpus(unsigned int max_cpus)
+void __init plat_smp_setup(void)
{
+ int i;
+
cpus_clear(phys_cpu_present_map);
- /*
- * The boot CPU
- */
- cpu_set(0, phys_cpu_present_map);
- __cpu_number_map[0] = 0;
- __cpu_logical_map[0] = 0;
+ for (i = 0; i < 2; i++) {
+ cpu_set(i, phys_cpu_present_map);
+ __cpu_number_map[i] = i;
+ __cpu_logical_map[i] = i;
+ }
+}
+void __init plat_prepare_cpus(unsigned int max_cpus)
+{
/*
- * The secondary core
+ * Be paranoid. Enable the IPI only if we're really about to go SMP.
*/
- cpu_set(1, phys_cpu_present_map);
- __cpu_number_map[1] = 1;
- __cpu_logical_map[1] = 1;
+ if (cpus_weight(cpu_possible_map))
+ set_c0_status(STATUSF_IP5);
}
/*
*/
void prom_boot_secondary(int cpu, struct task_struct *idle)
{
- unsigned long gp = (unsigned long) idle->thread_info;
- unsigned long sp = gp + THREAD_SIZE - 32;
+ unsigned long gp = (unsigned long) task_thread_info(idle);
+ unsigned long sp = __KSTK_TOS(idle);
secondary_sp = sp;
secondary_gp = gp;
{
}
-asmlinkage void titan_mailbox_irq(struct pt_regs *regs)
+asmlinkage void titan_mailbox_irq(void)
{
int cpu = smp_processor_id();
unsigned long status;