/*
* Interrupt handing routines for NEC VR4100 series.
*
- * Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ * Copyright (C) 2005-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <asm/irq_cpu.h>
#include <asm/system.h>
-#include <asm/vr41xx/vr41xx.h>
+#include <asm/vr41xx/irq.h>
typedef struct irq_cascade {
- int (*get_irq)(unsigned int, struct pt_regs *);
+ int (*get_irq)(unsigned int);
} irq_cascade_t;
static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
.name = "cascade",
};
-int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *))
+int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
{
int retval = 0;
EXPORT_SYMBOL_GPL(cascade_irq);
-asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs)
+static void irq_dispatch(unsigned int irq)
{
irq_cascade_t *cascade;
- irq_desc_t *desc;
+ struct irq_desc *desc;
if (irq >= NR_IRQS) {
atomic_inc(&irq_err_count);
if (cascade->get_irq != NULL) {
unsigned int source_irq = irq;
desc = irq_desc + source_irq;
- desc->handler->ack(source_irq);
- irq = cascade->get_irq(irq, regs);
+ if (desc->chip->mask_ack)
+ desc->chip->mask_ack(source_irq);
+ else {
+ desc->chip->mask(source_irq);
+ desc->chip->ack(source_irq);
+ }
+ irq = cascade->get_irq(irq);
if (irq < 0)
atomic_inc(&irq_err_count);
else
- irq_dispatch(irq, regs);
- desc->handler->end(source_irq);
+ irq_dispatch(irq);
+ if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
+ desc->chip->unmask(source_irq);
} else
- do_IRQ(irq, regs);
+ do_IRQ(irq);
}
-extern asmlinkage void vr41xx_handle_interrupt(void);
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+ if (pending & CAUSEF_IP7)
+ do_IRQ(7);
+ else if (pending & 0x7800) {
+ if (pending & CAUSEF_IP3)
+ irq_dispatch(3);
+ else if (pending & CAUSEF_IP4)
+ irq_dispatch(4);
+ else if (pending & CAUSEF_IP5)
+ irq_dispatch(5);
+ else if (pending & CAUSEF_IP6)
+ irq_dispatch(6);
+ } else if (pending & CAUSEF_IP2)
+ irq_dispatch(2);
+ else if (pending & CAUSEF_IP0)
+ do_IRQ(0);
+ else if (pending & CAUSEF_IP1)
+ do_IRQ(1);
+ else
+ spurious_interrupt();
+}
void __init arch_init_irq(void)
{
mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
-
- set_except_vector(0, vr41xx_handle_interrupt);
}