#include <linux/mm.h>
#include <linux/module.h>
#include <linux/seq_file.h>
+#include <linux/pagemap.h>
#include <asm/pdc.h>
#include <asm/cache.h>
int icache_stride;
EXPORT_SYMBOL(dcache_stride);
+
+#if defined(CONFIG_SMP)
+/* On some machines (e.g. ones with the Merced bus), there can be
+ * only a single PxTLB broadcast at a time; this must be guaranteed
+ * by software. We put a spinlock around all TLB flushes to
+ * ensure this.
+ */
+DEFINE_SPINLOCK(pa_tlb_lock);
+EXPORT_SYMBOL(pa_tlb_lock);
+#endif
+
struct pdc_cache_info cache_info;
#ifndef CONFIG_PA20
static struct pdc_btlb_info btlb_info;
{
on_each_cpu((void (*)(void *))flush_data_cache_local, NULL, 1, 1);
}
+void
+flush_instruction_cache(void)
+{
+ on_each_cpu((void (*)(void *))flush_instruction_cache_local, NULL, 1, 1);
+}
#endif
void
{
struct page *page = pte_page(pte);
- if (VALID_PAGE(page) && page_mapping(page) &&
+ if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
test_bit(PG_dcache_dirty, &page->flags)) {
flush_kernel_dcache_page(page_address(page));
{
seq_printf(m, "I-cache\t\t: %ld KB\n",
cache_info.ic_size/1024 );
- seq_printf(m, "D-cache\t\t: %ld KB (%s)%s\n",
+ seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %d-way associative)\n",
cache_info.dc_size/1024,
(cache_info.dc_conf.cc_wt ? "WT":"WB"),
- (cache_info.dc_conf.cc_sh ? " - shared I/D":"")
+ (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
+ (cache_info.dc_conf.cc_assoc)
);
seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
panic("parisc_cache_init: pdc_cache_info failed");
#if 0
- printk(KERN_DEBUG "ic_size %lx dc_size %lx it_size %lx pdc_cache_info %d*long pdc_cache_cf %d\n",
- cache_info.ic_size,
- cache_info.dc_size,
- cache_info.it_size,
- sizeof (struct pdc_cache_info) / sizeof (long),
- sizeof (struct pdc_cache_cf)
- );
-
- printk(KERN_DEBUG "dc base %x dc stride %x dc count %x dc loop %d\n",
- cache_info.dc_base,
- cache_info.dc_stride,
- cache_info.dc_count,
- cache_info.dc_loop);
-
- printk(KERN_DEBUG "dc conf: alias %d block %d line %d wt %d sh %d cst %d assoc %d\n",
- cache_info.dc_conf.cc_alias,
- cache_info.dc_conf.cc_block,
- cache_info.dc_conf.cc_line,
- cache_info.dc_conf.cc_wt,
- cache_info.dc_conf.cc_sh,
- cache_info.dc_conf.cc_cst,
- cache_info.dc_conf.cc_assoc);
-
- printk(KERN_DEBUG "ic conf: alias %d block %d line %d wt %d sh %d cst %d assoc %d\n",
- cache_info.ic_conf.cc_alias,
- cache_info.ic_conf.cc_block,
- cache_info.ic_conf.cc_line,
- cache_info.ic_conf.cc_wt,
- cache_info.ic_conf.cc_sh,
- cache_info.ic_conf.cc_cst,
- cache_info.ic_conf.cc_assoc);
-
- printk(KERN_DEBUG "dt conf: sh %d page %d cst %d aid %d pad1 %d \n",
- cache_info.dt_conf.tc_sh,
- cache_info.dt_conf.tc_page,
- cache_info.dt_conf.tc_cst,
- cache_info.dt_conf.tc_aid,
- cache_info.dt_conf.tc_pad1);
-
- printk(KERN_DEBUG "it conf: sh %d page %d cst %d aid %d pad1 %d \n",
- cache_info.it_conf.tc_sh,
- cache_info.it_conf.tc_page,
- cache_info.it_conf.tc_cst,
- cache_info.it_conf.tc_aid,
- cache_info.it_conf.tc_pad1);
+ printk("ic_size %lx dc_size %lx it_size %lx\n",
+ cache_info.ic_size,
+ cache_info.dc_size,
+ cache_info.it_size);
+
+ printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
+ cache_info.dc_base,
+ cache_info.dc_stride,
+ cache_info.dc_count,
+ cache_info.dc_loop);
+
+ printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
+ *(unsigned long *) (&cache_info.dc_conf),
+ cache_info.dc_conf.cc_alias,
+ cache_info.dc_conf.cc_block,
+ cache_info.dc_conf.cc_line,
+ cache_info.dc_conf.cc_shift);
+ printk(" wt %d sh %d cst %d assoc %d\n",
+ cache_info.dc_conf.cc_wt,
+ cache_info.dc_conf.cc_sh,
+ cache_info.dc_conf.cc_cst,
+ cache_info.dc_conf.cc_assoc);
+
+ printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
+ cache_info.ic_base,
+ cache_info.ic_stride,
+ cache_info.ic_count,
+ cache_info.ic_loop);
+
+ printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
+ *(unsigned long *) (&cache_info.ic_conf),
+ cache_info.ic_conf.cc_alias,
+ cache_info.ic_conf.cc_block,
+ cache_info.ic_conf.cc_line,
+ cache_info.ic_conf.cc_shift);
+ printk(" wt %d sh %d cst %d assoc %d\n",
+ cache_info.ic_conf.cc_wt,
+ cache_info.ic_conf.cc_sh,
+ cache_info.ic_conf.cc_cst,
+ cache_info.ic_conf.cc_assoc);
+
+ printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
+ cache_info.dt_conf.tc_sh,
+ cache_info.dt_conf.tc_page,
+ cache_info.dt_conf.tc_cst,
+ cache_info.dt_conf.tc_aid,
+ cache_info.dt_conf.tc_pad1);
+
+ printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
+ cache_info.it_conf.tc_sh,
+ cache_info.it_conf.tc_page,
+ cache_info.it_conf.tc_cst,
+ cache_info.it_conf.tc_aid,
+ cache_info.it_conf.tc_pad1);
#endif
split_tlb = 0;
split_tlb = 1;
}
- dcache_stride = (1 << (cache_info.dc_conf.cc_block + 3)) *
- cache_info.dc_conf.cc_line;
- icache_stride = (1 << (cache_info.ic_conf.cc_block + 3)) *
- cache_info.ic_conf.cc_line;
+ /* "New and Improved" version from Jim Hull
+ * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
+ */
+#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
+ dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
+ icache_stride = CAFL_STRIDE(cache_info.ic_conf);
+#undef CAFL_STRIDE
+
#ifndef CONFIG_PA20
if (pdc_btlb_info(&btlb_info) < 0) {
memset(&btlb_info, 0, sizeof btlb_info);
if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
PDC_MODEL_NVA_UNSUPPORTED) {
- printk(KERN_WARNING "Only equivalent aliasing supported\n");
-#ifndef CONFIG_SMP
+ printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
+#if 0
panic("SMP kernel required to avoid non-equivalent aliasing");
#endif
}
disable_sr_hashing_asm(srhash_type);
}
-void __flush_dcache_page(struct page *page)
+void flush_dcache_page(struct page *page)
{
struct address_space *mapping = page_mapping(page);
- struct mm_struct *mm = current->active_mm;
- struct list_head *l;
+ struct vm_area_struct *mpnt;
+ struct prio_tree_iter iter;
+ unsigned long offset;
+ unsigned long addr;
+ pgoff_t pgoff;
+ pte_t *pte;
+ unsigned long pfn = page_to_pfn(page);
- flush_kernel_dcache_page(page_address(page));
- if (!mapping)
+ if (mapping && !mapping_mapped(mapping)) {
+ set_bit(PG_dcache_dirty, &page->flags);
return;
- /* check shared list first if it's not empty...it's usually
- * the shortest */
- list_for_each(l, &mapping->i_mmap_shared) {
- struct vm_area_struct *mpnt;
- unsigned long off;
-
- mpnt = list_entry(l, struct vm_area_struct, shared);
-
- /*
- * If this VMA is not in our MM, we can ignore it.
- */
- if (mpnt->vm_mm != mm)
- continue;
-
- if (page->index < mpnt->vm_pgoff)
- continue;
-
- off = page->index - mpnt->vm_pgoff;
- if (off >= (mpnt->vm_end - mpnt->vm_start) >> PAGE_SHIFT)
- continue;
+ }
- flush_cache_page(mpnt, mpnt->vm_start + (off << PAGE_SHIFT));
+ flush_kernel_dcache_page(page_address(page));
- /* All user shared mappings should be equivalently mapped,
- * so once we've flushed one we should be ok
- */
+ if (!mapping)
return;
- }
- /* then check private mapping list for read only shared mappings
- * which are flagged by VM_MAYSHARE */
- list_for_each(l, &mapping->i_mmap) {
- struct vm_area_struct *mpnt;
- unsigned long off;
+ pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
- mpnt = list_entry(l, struct vm_area_struct, shared);
+ /* We have carefully arranged in arch_get_unmapped_area() that
+ * *any* mappings of a file are always congruently mapped (whether
+ * declared as MAP_PRIVATE or MAP_SHARED), so we only need
+ * to flush one address here for them all to become coherent */
+ flush_dcache_mmap_lock(mapping);
+ vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
+ offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
+ addr = mpnt->vm_start + offset;
- if (mpnt->vm_mm != mm || !(mpnt->vm_flags & VM_MAYSHARE))
- continue;
+ /* Flush instructions produce non access tlb misses.
+ * On PA, we nullify these instructions rather than
+ * taking a page fault if the pte doesn't exist.
+ * This is just for speed. If the page translation
+ * isn't there, there's no point exciting the
+ * nadtlb handler into a nullification frenzy */
- if (page->index < mpnt->vm_pgoff)
- continue;
- off = page->index - mpnt->vm_pgoff;
- if (off >= (mpnt->vm_end - mpnt->vm_start) >> PAGE_SHIFT)
+ if(!(pte = translation_exists(mpnt, addr)))
continue;
- flush_cache_page(mpnt, mpnt->vm_start + (off << PAGE_SHIFT));
+ /* make sure we really have this page: the private
+ * mappings may cover this area but have COW'd this
+ * particular page */
+ if(pte_pfn(*pte) != pfn)
+ continue;
+
+ __flush_cache_page(mpnt, addr);
- /* All user shared mappings should be equivalently mapped,
- * so once we've flushed one we should be ok
- */
break;
}
+ flush_dcache_mmap_unlock(mapping);
}
-EXPORT_SYMBOL(__flush_dcache_page);
+EXPORT_SYMBOL(flush_dcache_page);
/* Defined in arch/parisc/kernel/pacache.S */
EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
EXPORT_SYMBOL(flush_kernel_dcache_page);
EXPORT_SYMBOL(flush_data_cache_local);
EXPORT_SYMBOL(flush_kernel_icache_range_asm);
+
+void clear_user_page_asm(void *page, unsigned long vaddr)
+{
+ /* This function is implemented in assembly in pacache.S */
+ extern void __clear_user_page_asm(void *page, unsigned long vaddr);
+
+ purge_tlb_start();
+ __clear_user_page_asm(page, vaddr);
+ purge_tlb_end();
+}
+
+#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
+int parisc_cache_flush_threshold = FLUSH_THRESHOLD;
+
+void parisc_setup_cache_timing(void)
+{
+ unsigned long rangetime, alltime;
+ extern char _text; /* start of kernel code, defined by linker */
+ extern char _end; /* end of BSS, defined by linker */
+ unsigned long size;
+
+ alltime = mfctl(16);
+ flush_data_cache();
+ alltime = mfctl(16) - alltime;
+
+ size = (unsigned long)(&_end - _text);
+ rangetime = mfctl(16);
+ flush_kernel_dcache_range((unsigned long)&_text, size);
+ rangetime = mfctl(16) - rangetime;
+
+ printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
+ alltime, size, rangetime);
+
+ /* Racy, but if we see an intermediate value, it's ok too... */
+ parisc_cache_flush_threshold = size * alltime / rangetime;
+
+ parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
+ if (!parisc_cache_flush_threshold)
+ parisc_cache_flush_threshold = FLUSH_THRESHOLD;
+
+ printk("Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
+}
git://git.onelab.eu / linux-2.6.git / blobdiff