#define BITSSET 0x1c0 /* for identifying LDCW */
+
+DEFINE_PER_CPU(struct exception_data, exception_data);
+
/*
* parisc_acctyp(unsigned int inst) --
* Given a PA-RISC memory access instruction, determine if the
*/
switch (handle_mm_fault(mm, vma, address, (acc_type & VM_WRITE) != 0)) {
- case 1:
+ case VM_FAULT_MINOR:
++current->min_flt;
break;
- case 2:
+ case VM_FAULT_MAJOR:
++current->maj_flt;
break;
- case 0:
+ case VM_FAULT_SIGBUS:
/*
- * We ran out of memory, or some other thing happened
- * to us that made us unable to handle the page fault
- * gracefully.
+ * We hit a hared mapping outside of the file, or some
+ * other thing happened to us that made us unable to
+ * handle the page fault gracefully.
*/
goto bad_area;
default:
si.si_signo = SIGSEGV;
si.si_errno = 0;
si.si_code = SEGV_MAPERR;
- si.si_addr = (void *) address;
+ si.si_addr = (void __user *) address;
force_sig_info(SIGSEGV, &si, current);
return;
}
no_context:
if (!user_mode(regs)) {
-
fix = search_exception_tables(regs->iaoq[0]);
if (fix) {
+ struct exception_data *d;
- if (fix->skip & 1)
- regs->gr[8] = -EFAULT;
- if (fix->skip & 2)
- regs->gr[9] = 0;
+ d = &__get_cpu_var(exception_data);
+ d->fault_ip = regs->iaoq[0];
+ d->fault_space = regs->isr;
+ d->fault_addr = regs->ior;
- regs->iaoq[0] += ((fix->skip) & ~3);
+ regs->iaoq[0] = ((fix->fixup) & ~3);
/*
* NOTE: In some cases the faulting instruction