* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <linux/config.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/slab.h>
if (l == (1L << limit)) {
if (limit < 4) {
limit++;
- reg = DART_IN(DART_CNTL);
- reg &= ~inv_bit;
+ reg = DART_IN(DART_CNTL);
+ reg &= ~inv_bit;
DART_OUT(DART_CNTL, reg);
goto retry;
} else
}
}
-static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
-{
- unsigned int reg;
- unsigned int l, limit;
-
- reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
- (bus_rpn & DART_CNTL_U4_IONE_MASK);
- DART_OUT(DART_CNTL, reg);
-
- limit = 0;
-wait_more:
- l = 0;
- while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
- rmb();
- l++;
- }
-
- if (l == (1L << limit)) {
- if (limit < 4) {
- limit++;
- goto wait_more;
- } else
- panic("DART: TLB did not flush after waiting a long "
- "time. Buggy U4 ?");
- }
-}
-
static void dart_flush(struct iommu_table *tbl)
{
- mb();
- if (dart_dirty) {
+ if (dart_dirty)
dart_tlb_invalidate_all();
- dart_dirty = 0;
- }
+ dart_dirty = 0;
}
static void dart_build(struct iommu_table *tbl, long index,
{
unsigned int *dp;
unsigned int rpn;
- long l;
DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
/* On U3, all memory is contigous, so we can move this
* out of the loop.
*/
- l = npages;
- while (l--) {
+ while (npages--) {
rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
uaddr += DART_PAGE_SIZE;
}
- /* make sure all updates have reached memory */
- mb();
- in_be32((unsigned __iomem *)dp);
- mb();
-
- if (dart_is_u4) {
- rpn = index;
- while (npages--)
- dart_tlb_invalidate_one(rpn++);
- } else {
- dart_dirty = 1;
- }
+ dart_dirty = 1;
}
iommu_table_dart.it_base = (unsigned long)dart_vbase;
iommu_table_dart.it_index = 0;
iommu_table_dart.it_blocksize = 1;
- iommu_init_table(&iommu_table_dart, -1);
+ iommu_init_table(&iommu_table_dart);
/* Reserve the last page of the DART to avoid possible prefetch
* past the DART mapped area