vserver 1.9.5.x5

[linux-2.6.git] / arch / ppc / kernel / cpu_setup_6xx.S

diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index 9e4e48f..9a4ee63 100644 (file)
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -172,9 +172,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
 setup_750cx:
        mfspr   r10, SPRN_HID1
        rlwinm  r10,r10,4,28,31
-       cmpi    cr0,r10,7
-       cmpi    cr1,r10,9
-       cmpi    cr2,r10,11
+       cmpwi   cr0,r10,7
+       cmpwi   cr1,r10,9
+       cmpwi   cr2,r10,11
        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr2+eq
        bnelr
@@ -218,7 +218,10 @@ setup_745x_specifics:
 
        /* All of the bits we have to set.....
         */
-       ori     r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_BTIC | HID0_LRSTK
+       ori     r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_LRSTK | HID0_BTIC
+BEGIN_FTR_SECTION
+       xori    r11,r11,HID0_BTIC
+END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
 BEGIN_FTR_SECTION
        oris    r11,r11,HID0_DPM@h      /* enable dynamic power mgmt */
 END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
@@ -284,18 +287,20 @@ _GLOBAL(__save_cpu_setup)
        /* Now deal with CPU type dependent registers */
        mfspr   r3,PVR
        srwi    r3,r3,16
-       cmpli   cr0,r3,0x8000   /* 7450 */
-       cmpli   cr1,r3,0x000c   /* 7400 */
-       cmpli   cr2,r3,0x800c   /* 7410 */
-       cmpli   cr3,r3,0x8001   /* 7455 */
-       cmpli   cr4,r3,0x8002   /* 7457 */
-       cmpli   cr5,r3,0x7000   /* 750FX */
+       cmplwi  cr0,r3,0x8000   /* 7450 */
+       cmplwi  cr1,r3,0x000c   /* 7400 */
+       cmplwi  cr2,r3,0x800c   /* 7410 */
+       cmplwi  cr3,r3,0x8001   /* 7455 */
+       cmplwi  cr4,r3,0x8002   /* 7457 */
+       cmplwi  cr5,r3,0x8003   /* 7447A */
+       cmplwi  cr6,r3,0x7000   /* 750FX */
        /* cr1 is 7400 || 7410 */
        cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
        /* cr0 is 74xx */
        cror    4*cr0+eq,4*cr0+eq,4*cr3+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
+       cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
        bne     1f
        /* Backup 74xx specific regs */
        mfspr   r4,SPRN_MSSCR0
@@ -313,14 +318,14 @@ _GLOBAL(__save_cpu_setup)
        mfspr   r4,SPRN_LDSTDB
        stw     r4,CS_LDSTDB(r5)
 1:
-       bne     cr5,1f
+       bne     cr6,1f
        /* Backup 750FX specific registers */
        mfspr   r4,SPRN_HID1
        stw     r4,CS_HID1(r5)
        /* If rev 2.x, backup HID2 */
        mfspr   r3,PVR
        andi.   r3,r3,0xff00
-       cmpi    cr0,r3,0x0200
+       cmpwi   cr0,r3,0x0200
        bne     1f
        mfspr   r4,SPRN_HID2
        stw     r4,CS_HID2(r5)
@@ -351,18 +356,20 @@ _GLOBAL(__restore_cpu_setup)
        /* Now deal with CPU type dependent registers */
        mfspr   r3,PVR
        srwi    r3,r3,16
-       cmpli   cr0,r3,0x8000   /* 7450 */
-       cmpli   cr1,r3,0x000c   /* 7400 */
-       cmpli   cr2,r3,0x800c   /* 7410 */
-       cmpli   cr3,r3,0x8001   /* 7455 */
-       cmpli   cr4,r3,0x8002   /* 7457 */
-       cmpli   cr5,r3,0x7000   /* 750FX */
+       cmplwi  cr0,r3,0x8000   /* 7450 */
+       cmplwi  cr1,r3,0x000c   /* 7400 */
+       cmplwi  cr2,r3,0x800c   /* 7410 */
+       cmplwi  cr3,r3,0x8001   /* 7455 */
+       cmplwi  cr4,r3,0x8002   /* 7457 */
+       cmplwi  cr5,r3,0x8003   /* 7447A */
+       cmplwi  cr6,r3,0x7000   /* 750FX */
        /* cr1 is 7400 || 7410 */
        cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
        /* cr0 is 74xx */
        cror    4*cr0+eq,4*cr0+eq,4*cr3+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
+       cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
        bne     2f
        /* Restore 74xx specific regs */
        lwz     r4,CS_MSSCR0(r5)
@@ -401,7 +408,7 @@ _GLOBAL(__restore_cpu_setup)
        mtspr   SPRN_LDSTDB,r4
        isync
        sync
-2:     bne     cr5,1f
+2:     bne     cr6,1f
        /* Restore 750FX specific registers
         * that is restore HID2 on rev 2.x and PLL config & switch
         * to PLL 0 on all
@@ -409,7 +416,7 @@ _GLOBAL(__restore_cpu_setup)
        /* If rev 2.x, restore HID2 with low voltage bit cleared */
        mfspr   r3,PVR
        andi.   r3,r3,0xff00
-       cmpi    cr0,r3,0x0200
+       cmpwi   cr0,r3,0x0200
        bne     4f
        lwz     r4,CS_HID2(r5)
        rlwinm  r4,r4,0,19,17
@@ -423,7 +430,7 @@ _GLOBAL(__restore_cpu_setup)
        mftbl   r5
 3:     mftbl   r6
        sub     r6,r6,r5
-       cmpli   cr0,r6,10000
+       cmplwi  cr0,r6,10000
        ble     3b
        /* Setup final PLL */
        mtspr   SPRN_HID1,r4