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VServer 1.9.2 (patch-2.6.8.1-vs1.9.2.diff)
[linux-2.6.git] / arch / ppc / kernel / cputable.c
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index b48744b..b60fa99 100644 (file)
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -34,7 +34,8 @@ extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* s
 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
 
 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
-                    !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4))
+                    !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
+                    !defined(CONFIG_BOOKE))
 
 /* This table only contains "desktop" CPUs, it need to be filled with embedded
  * ones as well...
@@ -54,7 +55,8 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
 #endif
 
 /* We need to mark all pages as being coherent if we're SMP or we
- * have a 754x and an MPC107 host bridge. */
+ * have a 754x and an MPC107 host bridge.
+ */
 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 #else
@@ -209,7 +211,15 @@ struct cpu_spec    cpu_specs[] = {
        32, 32,
        __setup_cpu_750fx
     },
-
+    {  /* 750GX */
+       0xffff0000, 0x70020000, "750GX",
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+       CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+       COMMON_PPC,
+       32, 32,
+       __setup_cpu_750fx
+    },
     {  /* 740/750 (L2CR bit need fixup for 740) */
        0xffff0000, 0x00080000, "740/750",
        CPU_FTR_COMMON |
@@ -254,7 +264,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -265,7 +275,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_L3_DISABLE_NAP,
+       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -275,7 +285,8 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+       CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -285,7 +296,8 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+       CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -296,7 +308,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -307,18 +319,40 @@ struct cpu_spec   cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
+       COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+       32, 32,
+       __setup_cpu_745x
+    },
+    {  /* 7447/7457 Rev 1.0 */
+       0xffffffff, 0x80020100, "7447/7457",
+       CPU_FTR_COMMON |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
     },
-    {  /* 7457 */
-       0xffff0000, 0x80020000, "7457",
+    {  /* 7447/7457 Rev 1.1 */
+       0xffffffff, 0x80020101, "7447/7457",
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+       COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+       32, 32,
+       __setup_cpu_745x
+    },
+    {  /* 7447/7457 Rev 1.2 and later */
+       0xffff0000, 0x80020000, "7447/7457",
+       CPU_FTR_COMMON |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -329,7 +363,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -342,6 +376,14 @@ struct cpu_spec    cpu_specs[] = {
        32, 32,
        __setup_cpu_603
     },
+    {  /* All G2_LE (603e core, plus some) have the same pvr */
+       0x7fff0000, 0x00820000, "G2_LE",
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+       COMMON_PPC,
+       32, 32,
+       __setup_cpu_603
+    },
     {  /* default match, we assume split I/D cache & TB (non-601)... */
        0x00000000, 0x00000000, "(generic PPC)",
        CPU_FTR_COMMON |
@@ -537,14 +579,24 @@ struct cpu_spec   cpu_specs[] = {
         32, 32,
         0, /*__setup_cpu_440 */
     },
-    { /* 440GX Rev. B1 (2.1) */
-        0xf0000fff, 0x50000852, "440GX Rev. B1 (2.1)",
+    { /* 440GX Rev. C */
+        0xf0000fff, 0x50000892, "440GX Rev. C",
         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
         32, 32,
         0, /*__setup_cpu_440 */
     },
 #endif /* CONFIG_44x */
+#ifdef CONFIG_E500
+    { /* e500 */
+        0xffff0000, 0x80200000, "e500",
+       /* xxx - galak: add CPU_FTR_CAN_DOZE */
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+        32, 32,
+        0, /*__setup_cpu_e500 */
+    },
+#endif
 #if !CLASSIC_PPC
     {  /* default match */
        0x00000000, 0x00000000, "(generic PPC)",
linux-2.6