* DPM can possibly interfere with the state machine in the processor
* that invalidates the L2 cache tags.
*/
- mfspr r8,HID0 /* Save HID0 in r8 */
+ mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
sync
- mtspr HID0,r4 /* Disable DPM */
+ mtspr SPRN_HID0,r4 /* Disable DPM */
sync
/* Get the current enable bit of the L2CR into r4 */
- mfspr r4,L2CR
+ mfspr r4,SPRN_L2CR
/* Tweak some bits */
rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
.balign L1_CACHE_LINE_SIZE
22:
sync
- mtspr L2CR,r3
+ mtspr SPRN_L2CR,r3
sync
b 23f
20:
/* Perform a global invalidation */
oris r3,r3,0x0020
sync
- mtspr L2CR,r3
+ mtspr SPRN_L2CR,r3
sync
isync /* For errata */
BEGIN_FTR_SECTION
/* On the 7450, we wait for the L2I bit to clear......
*/
-10: mfspr r3,L2CR
+10: mfspr r3,SPRN_L2CR
andis. r4,r3,0x0020
bne 10b
b 11f
END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
/* Wait for the invalidation to complete */
-3: mfspr r3,L2CR
+3: mfspr r3,SPRN_L2CR
rlwinm. r4,r3,0,31,31
bne 3b
11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
sync
- mtspr L2CR,r3
+ mtspr SPRN_L2CR,r3
sync
/* See if we need to enable the cache */
/* Enable the cache */
oris r3,r3,0x8000
- mtspr L2CR,r3
+ mtspr SPRN_L2CR,r3
sync
4:
/* Return the L2CR contents */
li r3,0
BEGIN_FTR_SECTION
- mfspr r3,L2CR
+ mfspr r3,SPRN_L2CR
END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
blr