vserver 1.9.3

[linux-2.6.git] / arch / ppc / kernel / misc.S

diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index bd006ca..55ca736 100644 (file)
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -214,7 +214,7 @@ _GLOBAL(low_choose_750fx_pll)
        mtmsr   r0
 
        /* If switching to PLL1, disable HID0:BTIC */
-       cmpli   cr0,r3,0
+       cmplwi  cr0,r3,0
        beq     1f
        mfspr   r5,HID0
        rlwinm  r5,r5,0,27,25
@@ -239,7 +239,7 @@ _GLOBAL(low_choose_750fx_pll)
        stw     r4,nap_save_hid1@l(r6)
 
        /* If switching to PLL0, enable HID0:BTIC */
-       cmpli   cr0,r3,0
+       cmplwi  cr0,r3,0
        bne     1f
        mfspr   r5,HID0
        ori     r5,r5,HID0_BTIC
@@ -253,6 +253,24 @@ _GLOBAL(low_choose_750fx_pll)
        mtmsr   r7
        blr
 
+_GLOBAL(low_choose_7447a_dfs)
+       /* Clear MSR:EE */
+       mfmsr   r7
+       rlwinm  r0,r7,0,17,15
+       mtmsr   r0
+       
+       /* Calc new HID1 value */
+       mfspr   r4,SPRN_HID1
+       insrwi  r4,r3,1,9       /* insert parameter into bit 9 */
+       sync
+       mtspr   SPRN_HID1,r4
+       sync
+       isync
+
+       /* Return */
+       mtmsr   r7
+       blr
+
 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
 
 /* void local_save_flags_ptr(unsigned long *flags) */
@@ -419,7 +437,24 @@ _GLOBAL(_tlbia)
        ble     1b
 
        isync
-#else /* !(CONFIG_40x || CONFIG_44x) */
+#elif defined(CONFIG_FSL_BOOKE)
+       /* Invalidate all entries in TLB0 */
+       li      r3, 0x04
+       tlbivax 0,3
+       /* Invalidate all entries in TLB1 */
+       li      r3, 0x0c
+       tlbivax 0,3
+       /* Invalidate all entries in TLB2 */
+       li      r3, 0x14
+       tlbivax 0,3
+       /* Invalidate all entries in TLB3 */
+       li      r3, 0x1c
+       tlbivax 0,3
+       msync
+#ifdef CONFIG_SMP
+       tlbsync
+#endif /* CONFIG_SMP */
+#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
 #if defined(CONFIG_SMP)
        rlwinm  r8,r1,0,0,18
        lwz     r8,TI_CPU(r8)
@@ -435,7 +470,7 @@ _GLOBAL(_tlbia)
        ori     r9,r9,mmu_hash_lock@l
        tophys(r9,r9)
 10:    lwarx   r7,0,r9
-       cmpi    0,r7,0
+       cmpwi   0,r7,0
        bne-    10b
        stwcx.  r8,0,r9
        bne-    10b
@@ -487,7 +522,20 @@ _GLOBAL(_tlbie)
        tlbwe   r3, r3, PPC44x_TLB_PAGEID
        isync
 10:
-#else /* !(CONFIG_40x || CONFIG_44x) */
+#elif defined(CONFIG_FSL_BOOKE)
+       rlwinm  r4, r3, 0, 0, 19
+       ori     r5, r4, 0x08    /* TLBSEL = 1 */
+       ori     r6, r4, 0x10    /* TLBSEL = 2 */
+       ori     r7, r4, 0x18    /* TLBSEL = 3 */
+       tlbivax 0, r4
+       tlbivax 0, r5
+       tlbivax 0, r6
+       tlbivax 0, r7
+       msync
+#if defined(CONFIG_SMP)
+       tlbsync
+#endif /* CONFIG_SMP */
+#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
 #if defined(CONFIG_SMP)
        rlwinm  r8,r1,0,0,18
        lwz     r8,TI_CPU(r8)
@@ -503,7 +551,7 @@ _GLOBAL(_tlbie)
        ori     r9,r9,mmu_hash_lock@l
        tophys(r9,r9)
 10:    lwarx   r7,0,r9
-       cmpi    0,r7,0
+       cmpwi   0,r7,0
        bne-    10b
        stwcx.  r8,0,r9
        bne-    10b
@@ -544,10 +592,14 @@ _GLOBAL(flush_instruction_cache)
        lis     r3, KERNELBASE@h
        iccci   0,r3
 #endif
+#elif CONFIG_FSL_BOOKE
+       mfspr   r3,SPRN_L1CSR1
+       ori     r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
+       mtspr   SPRN_L1CSR1,r3
 #else
        mfspr   r3,PVR
        rlwinm  r3,r3,16,16,31
-       cmpi    0,r3,1
+       cmpwi   0,r3,1
        beqlr                   /* for 601, do nothing */
        /* 603/604 processor - use invalidate-all bit in HID0 */
        mfspr   r3,HID0
@@ -565,10 +617,9 @@ _GLOBAL(flush_instruction_cache)
  * flush_icache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_icache_range)
-       mfspr   r5,PVR
-       rlwinm  r5,r5,16,16,31
-       cmpi    0,r5,1
-       beqlr                           /* for 601, do nothing */
+BEGIN_FTR_SECTION
+       blr                             /* for 601, do nothing */
+END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
        li      r5,L1_CACHE_LINE_SIZE-1
        andc    r3,r3,r5
        subf    r4,r3,r4
@@ -683,10 +734,9 @@ _GLOBAL(flush_dcache_all)
  *     void __flush_dcache_icache(void *page)
  */
 _GLOBAL(__flush_dcache_icache)
-       mfspr   r5,PVR
-       rlwinm  r5,r5,16,16,31
-       cmpi    0,r5,1
-       beqlr                                   /* for 601, do nothing */
+BEGIN_FTR_SECTION
+       blr                                     /* for 601, do nothing */
+END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
        rlwinm  r3,r3,0,0,19                    /* Get page base address */
        li      r4,4096/L1_CACHE_LINE_SIZE      /* Number of lines in a page */
        mtctr   r4
@@ -712,10 +762,9 @@ _GLOBAL(__flush_dcache_icache)
  *     void __flush_dcache_icache_phys(unsigned long physaddr)
  */
 _GLOBAL(__flush_dcache_icache_phys)
-       mfspr   r5,PVR
-       rlwinm  r5,r5,16,16,31
-       cmpi    0,r5,1
-       beqlr                                   /* for 601, do nothing */
+BEGIN_FTR_SECTION
+       blr                                     /* for 601, do nothing */
+END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
        mfmsr   r10
        rlwinm  r0,r10,0,28,26                  /* clear DR */
        mtmsr   r0
@@ -1047,7 +1096,7 @@ _GLOBAL(_get_SP)
  * and exceptions as if the cpu had performed the load or store.
  */
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_E500)
 _GLOBAL(cvt_fd)
        lfs     0,0(r3)
        stfd    0,0(r4)
@@ -1092,7 +1141,7 @@ _GLOBAL(kernel_thread)
        li      r4,0            /* new sp (unused) */
        li      r0,__NR_clone
        sc
-       cmpi    0,r3,0          /* parent or child? */
+       cmpwi   0,r3,0          /* parent or child? */
        bne     1f              /* return if parent */
        li      r0,0            /* make top-level stack frame */
        stwu    r0,-16(r1)