/*
- * arch/ppc/platforms/ocotea.c
+ * arch/ppc/platforms/4xx/ocotea.c
*
* Ocotea board specific routines
*
- * Matt Porter <mporter@mvista.com>
+ * Matt Porter <mporter@kernel.crashing.org>
*
- * Copyright 2003 MontaVista Software Inc.
+ * Copyright 2003-2005 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
+#include <asm/ocp.h>
#include <asm/pci-bridge.h>
#include <asm/time.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/ppc4xx_pic.h>
+#include <asm/ppcboot.h>
-extern void abort(void);
+#include <syslib/gen550.h>
+#include <syslib/ibm440gx_common.h>
+
+/*
+ * This is a horrible kludge, we eventually need to abstract this
+ * generic PHY stuff, so the standard phy mode defines can be
+ * easily used from arch code.
+ */
+#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
-/* Global Variables */
bd_t __res;
+static struct ibm44x_clocks clocks __initdata;
+
static void __init
ocotea_calibrate_decr(void)
{
unsigned int freq;
- freq = OCOTEA_SYSCLK;
-
- tb_ticks_per_jiffy = freq / HZ;
- tb_to_us = mulhwu_scale_factor(freq, 1000000);
-
- /* Set the time base to zero */
- mtspr(SPRN_TBWL, 0);
- mtspr(SPRN_TBWU, 0);
-
- /* Clear any pending timer interrupts */
- mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
+ if (mfspr(SPRN_CCR1) & CCR1_TCS)
+ freq = OCOTEA_TMR_CLK;
+ else
+ freq = clocks.cpu;
- /* Enable decrementer interrupt */
- mtspr(SPRN_TCR, TCR_DIE);
+ ibm44x_calibrate_decr(freq);
}
static int
{
seq_printf(m, "vendor\t\t: IBM\n");
seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
-
+ ibm440gx_show_cpuinfo(m);
return 0;
}
+
static inline int
ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
return PCI_IRQ_TABLE_LOOKUP;
}
+static void __init ocotea_set_emacdata(void)
+{
+ struct ocp_def *def;
+ struct ocp_func_emac_data *emacdata;
+ int i;
+
+ /*
+ * Note: Current rev. board only operates in Group 4a
+ * mode, so we always set EMAC0-1 for SMII and EMAC2-3
+ * for RGMII (though these could run in RTBI just the same).
+ *
+ * The FPGA reg 3 information isn't even suitable for
+ * determining the phy_mode, so if the board becomes
+ * usable in !4a, it will be necessary to parse an environment
+ * variable from the firmware or similar to properly configure
+ * the phy_map/phy_mode.
+ */
+ /* Set phy_map, phy_mode, and mac_addr for each EMAC */
+ for (i=0; i<4; i++) {
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
+ emacdata = def->additions;
+ if (i < 2) {
+ emacdata->phy_map = 0x00000001; /* Skip 0x00 */
+ emacdata->phy_mode = PHY_MODE_SMII;
+ }
+ else {
+ emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
+ emacdata->phy_mode = PHY_MODE_RGMII;
+ }
+ if (i == 0)
+ memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+ else if (i == 1)
+ memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
+ else if (i == 2)
+ memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
+ else if (i == 3)
+ memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
+ }
+}
+
#define PCIX_READW(offset) \
- (readw((u32)pcix_reg_base+offset))
+ (readw(pcix_reg_base+offset))
#define PCIX_WRITEW(value, offset) \
- (writew(value, (u32)pcix_reg_base+offset))
+ (writew(value, pcix_reg_base+offset))
#define PCIX_WRITEL(value, offset) \
- (writel(value, (u32)pcix_reg_base+offset))
+ (writel(value, pcix_reg_base+offset))
/*
* FIXME: This is only here to "make it work". This will move
{
void *pcix_reg_base;
- pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
+ pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
- port.irq = 0;
- port.uartclk = BASE_BAUD * 16;
+ port.irq = UART0_INT;
+ port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
printk("Early serial init of port 0 failed\n");
}
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(0, &port);
+#endif
+
port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
- port.irq = 1;
+ port.irq = UART1_INT;
+ port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(1, &port);
+#endif
}
static void __init
ocotea_setup_arch(void)
{
- unsigned char *addr;
- unsigned long long mac64;
-
- /* Retrieve MAC addresses from flash */
- addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE);
- mac64 = simple_strtoull(addr, 0, 16);
- memcpy(__res.bi_enetaddr[0], (char *)&mac64+2, 6);
- mac64 = simple_strtoull(addr+OCOTEA_MAC1_OFFSET, 0, 16);
- memcpy(__res.bi_enetaddr[1], (char *)&mac64+2, 6);
- iounmap(addr);
-
-#if !defined(CONFIG_BDI_SWITCH)
- /*
- * The Abatron BDI JTAG debugger does not tolerate others
- * mucking with the debug registers.
- */
- mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
-#endif
+ ocotea_set_emacdata();
+
+ ibm440gx_tah_enable();
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
ROOT_DEV = Root_HDA1;
#endif
-#ifdef CONFIG_DUMMY_CONSOLE
- conswitchp = &dummy_con;
-#endif
-
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
}
-static void
-ocotea_restart(char *cmd)
+static void __init ocotea_init(void)
{
- local_irq_disable();
- abort();
+ ibm440gx_l2c_setup(&clocks);
}
-static void
-ocotea_power_off(void)
-{
- local_irq_disable();
- for(;;);
-}
-
-static void
-ocotea_halt(void)
-{
- local_irq_disable();
- for(;;);
-}
-
-/*
- * Read the 440GX memory controller to get size of system memory.
- */
-static unsigned long __init
-ocotea_find_end_of_memory(void)
-{
- u32 i, bank_config;
- u32 mem_size = 0;
-
- for (i=0; i<4; i++)
- {
- switch (i)
- {
- case 0:
- mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
- break;
- case 1:
- mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
- break;
- case 2:
- mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
- break;
- case 3:
- mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
- break;
- }
-
- bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
-
- if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
- continue;
- switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
- {
- case SDRAM_CONFIG_SIZE_8M:
- mem_size += PPC44x_MEM_SIZE_8M;
- break;
- case SDRAM_CONFIG_SIZE_16M:
- mem_size += PPC44x_MEM_SIZE_16M;
- break;
- case SDRAM_CONFIG_SIZE_32M:
- mem_size += PPC44x_MEM_SIZE_32M;
- break;
- case SDRAM_CONFIG_SIZE_64M:
- mem_size += PPC44x_MEM_SIZE_64M;
- break;
- case SDRAM_CONFIG_SIZE_128M:
- mem_size += PPC44x_MEM_SIZE_128M;
- break;
- case SDRAM_CONFIG_SIZE_256M:
- mem_size += PPC44x_MEM_SIZE_256M;
- break;
- case SDRAM_CONFIG_SIZE_512M:
- mem_size += PPC44x_MEM_SIZE_512M;
- break;
- }
- }
- return mem_size;
-}
-
-static void __init
-ocotea_init_irq(void)
-{
- int i;
-
- /* Enable PPC440GP interrupt compatibility mode */
- SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) | DCRN_SDR_MFR_PCM);
-
- ppc4xx_pic_init();
-
- for (i = 0; i < NR_IRQS; i++)
- irq_desc[i].handler = ppc4xx_pic;
-}
-
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
-#include <linux/serialP.h>
-#include <linux/serial_reg.h>
-#include <asm/serial.h>
-struct serial_state rs_table[RS_TABLE_SIZE] = {
- SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
-};
-
-static void
-ocotea_progress(char *s, unsigned short hex)
+void __init platform_init(unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, unsigned long r7)
{
- volatile char c;
- volatile unsigned long com_port;
- u16 shift;
+ parse_bootinfo(find_bootinfo());
- com_port = (unsigned long)rs_table[0].iomem_base;
- shift = rs_table[0].iomem_reg_shift;
-
- while ((c = *s++) != 0) {
- while ((*((volatile unsigned char *)com_port +
- (UART_LSR << shift)) & UART_LSR_THRE) == 0)
- ;
- *(volatile unsigned char *)com_port = c;
-
- }
-
- /* Send LF/CR to pretty up output */
- while ((*((volatile unsigned char *)com_port +
- (UART_LSR << shift)) & UART_LSR_THRE) == 0)
- ;
- *(volatile unsigned char *)com_port = '\r';
- while ((*((volatile unsigned char *)com_port +
- (UART_LSR << shift)) & UART_LSR_THRE) == 0)
- ;
- *(volatile unsigned char *)com_port = '\n';
-}
-#endif /* CONFIG_SERIAL_TEXT_DEBUG */
+ /*
+ * If we were passed in a board information, copy it into the
+ * residual data area.
+ */
+ if (r3)
+ __res = *(bd_t *)(r3 + KERNELBASE);
-#if 0
-static void __init
-ocotea_map_io(void)
-{
- io_block_mapping(0xe0000000, 0x0000000140000000,
- 0x00001000, _PAGE_IO);
-}
-#endif
+ /*
+ * Determine various clocks.
+ * To be completely correct we should get SysClk
+ * from FPGA, because it can be changed by on-board switches
+ * --ebs
+ */
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
-void __init platform_init(unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, unsigned long r7)
-{
- parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
+ ibm44x_platform_init();
ppc_md.setup_arch = ocotea_setup_arch;
ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
- ppc_md.init_IRQ = ocotea_init_irq;
ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
- ppc_md.find_end_of_memory = ocotea_find_end_of_memory;
-
- ppc_md.restart = ocotea_restart;
- ppc_md.power_off = ocotea_power_off;
- ppc_md.halt = ocotea_halt;
-
ppc_md.calibrate_decr = ocotea_calibrate_decr;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
-
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
- ppc_md.progress = ocotea_progress;
-#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#ifdef CONFIG_KGDB
ppc_md.early_serial_map = ocotea_early_serial_map;
#endif
+ ppc_md.init = ocotea_init;
}
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