fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / ppc / platforms / 4xx / ocotea.c

diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index c981f70..84e999d 100644 (file)
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -1,11 +1,9 @@
 /*
- * arch/ppc/platforms/ocotea.c
- *
  * Ocotea board specific routines
  *
- * Matt Porter <mporter@mvista.com>
+ * Matt Porter <mporter@kernel.crashing.org>
  *
- * Copyright 2003 MontaVista Software Inc.
+ * Copyright 2003-2005 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -13,7 +11,6 @@
  * option) any later version.
  */
 
-#include <linux/config.h>
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -28,7 +25,6 @@
 #include <linux/delay.h>
 #include <linux/ide.h>
 #include <linux/initrd.h>
-#include <linux/irq.h>
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/tty.h>
@@ -48,17 +44,12 @@
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
+#include <asm/tlbflush.h>
 
+#include <syslib/gen550.h>
 #include <syslib/ibm440gx_common.h>
 
-/*
- * This is a horrible kludge, we eventually need to abstract this
- * generic PHY stuff, so the  standard phy mode defines can be
- * easily used from arch code.
- */
-#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
-
-bd_t __res;
+extern bd_t __res;
 
 static struct ibm44x_clocks clocks __initdata;
 
@@ -80,7 +71,7 @@ ocotea_show_cpuinfo(struct seq_file *m)
 {
        seq_printf(m, "vendor\t\t: IBM\n");
        seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
-
+       ibm440gx_show_cpuinfo(m);
        return 0;
 }
 
@@ -144,13 +135,13 @@ static void __init ocotea_set_emacdata(void)
 }
 
 #define PCIX_READW(offset) \
-       (readw((u32)pcix_reg_base+offset))
+       (readw(pcix_reg_base+offset))
 
 #define PCIX_WRITEW(value, offset) \
-       (writew(value, (u32)pcix_reg_base+offset))
+       (writew(value, pcix_reg_base+offset))
 
 #define PCIX_WRITEL(value, offset) \
-       (writel(value, (u32)pcix_reg_base+offset))
+       (writel(value, pcix_reg_base+offset))
 
 /*
  * FIXME: This is only here to "make it work".  This will move
@@ -162,7 +153,7 @@ ocotea_setup_pcix(void)
 {
        void *pcix_reg_base;
 
-       pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
+       pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 
        /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
        PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
@@ -226,9 +217,8 @@ ocotea_setup_hose(void)
        hose->io_space.end = OCOTEA_PCI_UPPER_IO;
        hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
        hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
-       isa_io_base =
-               (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
-       hose->io_base_virt = (void *)isa_io_base;
+       hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
+       isa_io_base = (unsigned long) hose->io_base_virt;
 
        setup_indirect_pci(hose,
                        OCOTEA_PCI_CFGA_PLB32,
@@ -255,14 +245,22 @@ ocotea_early_serial_map(void)
        port.irq = UART0_INT;
        port.uartclk = clocks.uart0;
        port.regshift = 0;
-       port.iotype = SERIAL_IO_MEM;
-       port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+       port.iotype = UPIO_MEM;
+       port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
        port.line = 0;
 
        if (early_serial_setup(&port) != 0) {
                printk("Early serial init of port 0 failed\n");
        }
 
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+       /* Configure debug serial access */
+       gen550_init(0, &port);
+
+       /* Purge TLB entry added in head_44x.S for early serial access */
+       _tlbie(UART0_IO_BASE);
+#endif
+
        port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
        port.irq = UART1_INT;
        port.uartclk = clocks.uart1;
@@ -271,6 +269,11 @@ ocotea_early_serial_map(void)
        if (early_serial_setup(&port) != 0) {
                printk("Early serial init of port 1 failed\n");
        }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+       /* Configure debug serial access */
+       gen550_init(1, &port);
+#endif
 }
 
 static void __init
@@ -280,14 +283,6 @@ ocotea_setup_arch(void)
 
        ibm440gx_tah_enable();
 
-#if !defined(CONFIG_BDI_SWITCH)
-       /*
-        * The Abatron BDI JTAG debugger does not tolerate others
-        * mucking with the debug registers.
-        */
-        mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
-#endif
-
        /*
         * Determine various clocks.
         * To be completely correct we should get SysClk
@@ -327,22 +322,15 @@ ocotea_setup_arch(void)
        printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
 }
 
+static void __init ocotea_init(void)
+{
+       ibm440gx_l2c_setup(&clocks);
+}
+
 void __init platform_init(unsigned long r3, unsigned long r4,
                unsigned long r5, unsigned long r6, unsigned long r7)
 {
-       parse_bootinfo(find_bootinfo());
-
-       /*
-        * If we were passed in a board information, copy it into the
-        * residual data area.
-        */
-       if (r3)
-               __res = *(bd_t *)(r3 + KERNELBASE);
-
-       /* Disable L2-Cache due to hardware issues */
-       ibm440gx_l2c_disable();
-
-       ibm44x_platform_init();
+       ibm440gx_platform_init(r3, r4, r5, r6, r7);
 
        ppc_md.setup_arch = ocotea_setup_arch;
        ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
@@ -355,8 +343,8 @@ void __init platform_init(unsigned long r3, unsigned long r4,
 
        ppc_md.nvram_read_val = todc_direct_read_val;
        ppc_md.nvram_write_val = todc_direct_write_val;
-
 #ifdef CONFIG_KGDB
        ppc_md.early_serial_map = ocotea_early_serial_map;
 #endif
+       ppc_md.init = ocotea_init;
 }