#include <linux/string.h>
#include <linux/init.h>
#include <linux/ide.h>
-#include <linux/bootmem.h>
#include <asm/io.h>
#include <asm/pgtable.h>
* limit the bus number to 3 bits
*/
-int __chrp gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
+int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
int len, u32 *val)
{
volatile void __iomem *cfg_data;
return PCIBIOS_SUCCESSFUL;
}
-int __chrp gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
+int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
int len, u32 val)
{
volatile void __iomem *cfg_data;
/*
* Access functions for PCI config space using RTAS calls.
*/
-int __chrp
+int
rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}
-int __chrp
+int
rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
rtas_write_config
};
-volatile struct Hydra *Hydra = NULL;
+volatile struct Hydra __iomem *Hydra = NULL;
int __init
hydra_init(void)
static void __init
setup_python(struct pci_controller *hose, struct device_node *dev)
{
- u32 *reg, val;
+ u32 __iomem *reg;
+ u32 val;
unsigned long addr = dev->addrs[0].address;
setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
/* Clear the magic go-slow bit */
- reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
+ reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40);
val = in_be32(®[12]);
if (val & PRG_CL_RESET_VALID) {
out_be32(®[12], val & ~PRG_CL_RESET_VALID);
printk ("RTAS supporting Pegasos OF not found, please upgrade"
" your firmware\n");
}
- pci_assign_all_busses = 1;
+ pci_assign_all_buses = 1;
}
void __init
setup_python(hose, dev);
} else if (is_mot
|| strncmp(model, "Motorola, Grackle", 17) == 0) {
- setup_grackle(hose);
+ setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
} else if (is_longtrail) {
void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
hose->ops = &gg2_pci_ops;