return 0;
}
-static u32
-lopec_irq_canonicalize(u32 irq)
-{
- if (irq == 2)
- return 9;
- else
- return irq;
-}
-
static void
lopec_restart(char *cmd)
{
static void
lopec_ide_probe(void)
{
- struct pci_dev *dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
+ struct pci_dev *dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_82C105,
NULL);
lopec_ide_ports_known = 1;
lopec_ide_ctl_regbase[0] = dev->resource[1].start;
lopec_ide_ctl_regbase[1] = dev->resource[3].start;
lopec_idedma_regbase = dev->resource[4].start;
+ pci_dev_put(dev);
}
}
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
&i8259_irq);
- /* Map i8259 interrupts */
- for(i = 0; i < NUM_8259_INTERRUPTS; i++)
- irq_desc[i].handler = &i8259_pic;
-
/*
* The EPIC allows for a read in the range of 0xFEF00000 ->
* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
*/
- i8259_init(0xfef00000);
+ i8259_init(0xfef00000, 0);
}
static int __init
lopec_set_bat(void)
{
mb();
- mtspr(DBAT1U, 0xf8000ffe);
- mtspr(DBAT1L, 0xf800002a);
+ mtspr(SPRN_DBAT1U, 0xf8000ffe);
+ mtspr(SPRN_DBAT1L, 0xf800002a);
mb();
}
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
+ ppc_do_canonicalize_irqs = 1;
ppc_md.setup_arch = lopec_setup_arch;
ppc_md.show_cpuinfo = lopec_show_cpuinfo;
- ppc_md.irq_canonicalize = lopec_irq_canonicalize;
ppc_md.init_IRQ = lopec_init_IRQ;
ppc_md.get_irq = openpic_get_irq;