/* use the gt64260 for all (possible) interrupt sources */
for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++)
- irq_desc[i].chip = >64260_pic;
+ irq_desc[i].handler = >64260_pic;
if (ppc_md.progress)
ppc_md.progress("gt64260_init_irq: exit", 0x0);
/* Register CPU interface error interrupt handler */
if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
- gt64260_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0)))
+ gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
/* Register PCI 0 error interrupt handler */
if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
- IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
+ SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
printk(KERN_WARNING "Can't register pci 0 error handler: %d",
rc);
/* Register PCI 1 error interrupt handler */
if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
- IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
+ SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
printk(KERN_WARNING "Can't register pci 1 error handler: %d",
rc);