fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / ppc / syslib / ibm440gx_common.c

diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c
index 5da7bca..6ad52f4 100644 (file)
--- a/arch/ppc/syslib/ibm440gx_common.c
+++ b/arch/ppc/syslib/ibm440gx_common.c
@@ -1,10 +1,8 @@
 /*
- * arch/ppc/kernel/ibm440gx_common.c
- *
  * PPC440GX system library
  *
  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003 Zultys Technologies
+ * Copyright (c) 2003 - 2006 Zultys Technologies
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -12,8 +10,8 @@
  * option) any later version.
  *
  */
-#include <linux/config.h>
 #include <linux/kernel.h>
+#include <linux/interrupt.h>
 #include <asm/ibm44x.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
@@ -33,6 +31,10 @@ void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,
        u32 plld  = CPR_READ(DCRN_CPR_PLLD);
        u32 uart0 = SDR_READ(DCRN_SDR_UART0);
        u32 uart1 = SDR_READ(DCRN_SDR_UART1);
+#ifdef CONFIG_440EP
+       u32 uart2 = SDR_READ(DCRN_SDR_UART2);
+       u32 uart3 = SDR_READ(DCRN_SDR_UART3);
+#endif
 
        /* Dividers */
        u32 fbdv   = __fix_zero((plld >> 24) & 0x1f, 32);
@@ -95,12 +97,64 @@ bypass:
                p->uart1 = ser_clk;
        else
                p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+#ifdef CONFIG_440EP
+       if (uart2 & 0x00800000)
+               p->uart2 = ser_clk;
+       else
+               p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256);
+
+       if (uart3 & 0x00800000)
+               p->uart3 = ser_clk;
+       else
+               p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256);
+#endif
+}
+
+/* Issue L2C diagnostic command */
+static inline u32 l2c_diag(u32 addr)
+{
+       mtdcr(DCRN_L2C0_ADDR, addr);
+       mtdcr(DCRN_L2C0_CMD, L2C_CMD_DIAG);
+       while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ;
+       return mfdcr(DCRN_L2C0_DATA);
+}
+
+static irqreturn_t l2c_error_handler(int irq, void* dev)
+{
+       u32 sr = mfdcr(DCRN_L2C0_SR);
+       if (sr & L2C_SR_CPE){
+               /* Read cache trapped address */
+               u32 addr = l2c_diag(0x42000000);
+               printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n", addr);
+       }
+       if (sr & L2C_SR_TPE){
+               /* Read tag trapped address */
+               u32 addr = l2c_diag(0x82000000) >> 16;
+               printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n", addr);
+       }
+
+       /* Clear parity errors */
+       if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
+               mtdcr(DCRN_L2C0_ADDR, 0);
+               mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
+       } else
+               printk(KERN_EMERG "L2C: LRU error\n");
+
+       return IRQ_HANDLED;
 }
 
-/* Enable L2 cache (call with IRQs disabled) */
+/* Enable L2 cache */
 void __init ibm440gx_l2c_enable(void){
        u32 r;
+       unsigned long flags;
 
+       /* Install error handler */
+       if (request_irq(87, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0){
+               printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n");
+               return;
+       }
+
+       local_irq_save(flags);
        asm volatile ("sync" ::: "memory");
 
        /* Disable SRAM */
@@ -137,20 +191,22 @@ void __init ibm440gx_l2c_enable(void){
 
        /* Enable ICU/DCU ports */
        r = mfdcr(DCRN_L2C0_CFG);
-       r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM
-               | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM | L2C_CFG_TPEI | L2C_CFG_CPEI
-               | L2C_CFG_NAM | L2C_CFG_NBRM);
+       r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM | L2C_CFG_TPEI
+               | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
        r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
-               | L2C_CFG_SMCM;
+               | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
        mtdcr(DCRN_L2C0_CFG, r);
 
        asm volatile ("sync; isync" ::: "memory");
+       local_irq_restore(flags);
 }
 
-/* Disable L2 cache (call with IRQs disabled) */
+/* Disable L2 cache */
 void __init ibm440gx_l2c_disable(void){
        u32 r;
+       unsigned long flags;
 
+       local_irq_save(flags);
        asm volatile ("sync" ::: "memory");
 
        /* Disable L2C mode */
@@ -169,6 +225,21 @@ void __init ibm440gx_l2c_disable(void){
              SRAM_SBCR_BAS3 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
 
        asm volatile ("sync; isync" ::: "memory");
+       local_irq_restore(flags);
+}
+
+void __init ibm440gx_l2c_setup(struct ibm44x_clocks* p)
+{
+       /* Disable L2C on rev.A, rev.B and 800MHz version of rev.C,
+          enable it on all other revisions
+        */
+       if (strcmp(cur_cpu_spec->cpu_name, "440GX Rev. A") == 0 ||
+                       strcmp(cur_cpu_spec->cpu_name, "440GX Rev. B") == 0
+                       || (strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C")
+                               == 0 && p->cpu > 667000000))
+               ibm440gx_l2c_disable();
+       else
+               ibm440gx_l2c_enable();
 }
 
 int __init ibm440gx_get_eth_grp(void)
@@ -210,3 +281,14 @@ int ibm440gx_show_cpuinfo(struct seq_file *m){
        return 0;
 }
 
+void __init ibm440gx_platform_init(unsigned long r3, unsigned long r4,
+                                  unsigned long r5, unsigned long r6,
+                                  unsigned long r7)
+{
+       /* Erratum 440_43 workaround, disable L1 cache parity checking */
+       if (!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C") ||
+           !strcmp(cur_cpu_spec->cpu_name, "440GX Rev. F"))
+               mtspr(SPRN_CCR1, mfspr(SPRN_CCR1) | CCR1_DPC);
+
+       ibm44x_platform_init(r3, r4, r5, r6, r7);
+}